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    Integrated circuit structures for increasing resistance to single event upset
    1.
    发明申请
    Integrated circuit structures for increasing resistance to single event upset 有权
    集成电路结构，增加对单一事件的不耐烦

    公开(公告)号：US20060001045A1

    公开(公告)日：2006-01-05

    申请号：US10883091

    申请日：2004-07-01

    申请人： Lakhbeer Sidhu ,  Irfan Rahim ,  Jeffrey Watt ,  John Turner

    发明人： Lakhbeer Sidhu ,  Irfan Rahim ,  Jeffrey Watt ,  John Turner

    IPC分类号： H01L29/739 ,  H01L27/10 ,  G11C16/04 ,  G11C11/34

    CPC分类号： G11C11/412 ,  H01L27/0207 ,  H01L27/11807

    摘要： A configuration memory cell (“CRAM”) for a field programmable gate array (“FPGA”) integrated circuit (“IC”) device is given increased resistance to single event upset (“SEU”). A portion of the gate structure of the input node of the CRAM is increased in size relative to the nominal size of the remainder of the gate structure. Part of the enlarged gate structure is located capacitively adjacent to an N-well region of the IC, and another part is located capacitively adjacent to a P-well region of the IC. This arrangement gives the input node increased capacitance to resist SEU, regardless of the logical level of the input node. The invention is also applicable to any node of any type of memory cell for which increased resistance to SEU is desired.

    摘要翻译： 用于现场可编程门阵列（“FPGA”）集成电路（“IC”）器件的配置存储单元（“CRAM”）被赋予增加的对单一事件不正常（“SEU”）的阻力。 CRAM的输入节点的栅极结构的一部分相对于栅极结构的其余部分的标称尺寸增大。 放大栅极结构的一部分位于与IC的N阱区电容性相邻的位置，另一部分位于与IC的P阱区电容相邻的位置。 这种布置使得输入节点增加了抵抗SEU的电容，而与输入节点的逻辑电平无关。 本发明也可应用于任何类型的存储器单元的任何节点，其对期望增加的对SEU的抗性。

    INTEGRATED CIRCUIT STRUCTURES FOR INCREASING RESISTANCE TO SINGLE EVENT UPSET
    2.
    发明申请
    INTEGRATED CIRCUIT STRUCTURES FOR INCREASING RESISTANCE TO SINGLE EVENT UPSET 有权
    集成电路结构，增加了对单一事件的抵抗力

    公开(公告)号：US20080074145A1

    公开(公告)日：2008-03-27

    申请号：US11951122

    申请日：2007-12-05

    申请人： Lakhbeer Sidhu ,  Irfan Rahim ,  Jeffrey Watt ,  John Turner

    发明人： Lakhbeer Sidhu ,  Irfan Rahim ,  Jeffrey Watt ,  John Turner

    IPC分类号： H03K19/173

    CPC分类号： G11C11/412 ,  H01L27/0207 ,  H01L27/11807

    摘要： A configuration memory cell (“CRAM”) for a field programmable gate array (“FPGA”) integrated circuit (“IC”) device is given increased resistance to single event upset (“SEU”). A portion of the gate structure of the input node of the CRAM is increased in size relative to the nominal size of the remainder of the gate structure. Part of the enlarged gate structure is located capacitively adjacent to an N-well region of the IC, and another part is located capacitively adjacent to a P-well region of the IC. This arrangement gives the input node increased capacitance to resist SEU, regardless of the logical level of the input node. The invention is also applicable to any node of any type of memory cell for which increased resistance to SEU is desired.

    摘要翻译： 用于现场可编程门阵列（“FPGA”）集成电路（“IC”）器件的配置存储单元（“CRAM”）被赋予增加的对单一事件不正常（“SEU”）的阻力。 CRAM的输入节点的栅极结构的一部分相对于栅极结构的其余部分的标称尺寸增大。 放大栅极结构的一部分位于与IC的N阱区电容性相邻的位置，另一部分位于与IC的P阱区电容相邻的位置。 这种布置使得输入节点增加了抵抗SEU的电容，而与输入节点的逻辑电平无关。 本发明也可应用于任何类型的存储器单元的任何节点，其对期望增加的对SEU的抗性。

    Integrated circuit structures for increasing resistance to single event upset
    3.
    发明授权
    Integrated circuit structures for increasing resistance to single event upset 有权

    公开(公告)号：US07465971B2

    公开(公告)日：2008-12-16

    申请号：US11951122

    申请日：2007-12-05

    申请人： Lakhbeer S. Sidhu ,  Irfan Rahim ,  Jeffrey Watt ,  John Turner

    发明人： Lakhbeer S. Sidhu ,  Irfan Rahim ,  Jeffrey Watt ,  John Turner

    IPC分类号： H01L29/94

    CPC分类号： G11C11/412 ,  H01L27/0207 ,  H01L27/11807

    摘要： A configuration memory cell (“CRAM”) for a field programmable gate array (“FPGA”) integrated circuit (“IC”) device is given increased resistance to single event upset (“SEU”). A portion of the gate structure of the input node of the CRAM is increased in size relative to the nominal size of the remainder of the gate structure. Part of the enlarged gate structure is located capacitively adjacent to an N-well region of the IC, and another part is located capacitively adjacent to a P-well region of the IC. This arrangement gives the input node increased capacitance to resist SEU, regardless of the logical level of the input node. The invention is also applicable to any node of any type of memory cell for which increased resistance to SEU is desired.

    Lockable package with slide tray
    6.
    发明授权
    Lockable package with slide tray 有权
    带滑动托盘的可锁定包装

    公开(公告)号：US08235204B2

    公开(公告)日：2012-08-07

    申请号：US12630598

    申请日：2009-12-03

    申请人： Robert Loughman ,  John Turner ,  George Howell

    发明人： Robert Loughman ,  John Turner ,  George Howell

    IPC分类号： A45C13/10

    CPC分类号： B65D5/38 ,  B65D5/4204 ,  B65D2215/02 ,  B65D2583/0468

    摘要： A lockable package includes an outer sleeve defined by connected first and second panels, the sleeve having at least one open end. An inner container is slidable within the sleeve, and having a first portion joined to a second portion, wherein at least one of a height and a width of the first portion is less than a corresponding height and width of the second portion. A difference between one of the height and the width of the first portion and the corresponding height and width of the second portion defines a ridge. A locking assembly is provided at the at least one open end of the sleeve and is configured to releasably engage the ridge, wherein the inner container is removable through the open end of the sleeve by disengaging the locking assembly from the ridge.

    摘要翻译： 可锁定包装包括由连接的第一和第二面板限定的外部套筒，所述套筒具有至少一个开口端。 内部容器可在套筒内滑动，并且具有连接到第二部分的第一部分，其中第一部分的高度和宽度中的至少一个小于第二部分的对应高度和宽度。 第一部分的高度和宽度之一与第二部分的对应高度和宽度之间的差异限定了一个脊。 锁定组件设置在套筒的至少一个开口端处，并且构造成可释放地接合脊部，其中通过使锁定组件与脊部脱离，内部容器可以通过套筒的开口端移除。

    Surface modified stainless steels for PEM fuel cell bipolar plates
    10.
    发明申请
    Surface modified stainless steels for PEM fuel cell bipolar plates 有权
    用于PEM燃料电池双极板的表面改性不锈钢

    公开(公告)号：US20050238873A1

    公开(公告)日：2005-10-27

    申请号：US11071830

    申请日：2005-03-03

    申请人： Michael Brady ,  Heli Wang ,  John Turner

    发明人： Michael Brady ,  Heli Wang ,  John Turner

    IPC分类号： B32B9/00 ,  B32B15/00 ,  C23C8/26

    CPC分类号： C23C8/26 ,  Y10T428/265

    摘要： A nitridation treated stainless steel article (such as a bipolar plate for a proton exchange membrane fuel cell) having lower interfacial contact electrical resistance and better corrosion resistance than an untreated stainless steel article is disclosed. The treated stainless steel article has a surface layer including nitrogen-modified chromium-base oxide and precipitates of chromium nitride formed during nitridation wherein oxygen is present in the surface layer at a greater concentration than nitrogen. The surface layer may further include precipitates of titanium nitride and/or aluminum oxide. The surface layer in the treated article is chemically heterogeneous surface rather than a uniform or semi-uniform surface layer exclusively rich in chromium, titanium or aluminum. The precipitates of titanium nitride and/or aluminum oxide are formed by the nitriding treatment wherein titanium and/or aluminum in the stainless steel are segregated to the surface layer in forms that exhibit a low contact resistance and good corrosion resistance.

    摘要翻译： 公开了一种氮化处理的不锈钢制品（例如用于质子交换膜燃料电池的双极板），其具有比未处理的不锈钢制品更低的界面接触电阻和更好的耐腐蚀性。 经处理的不锈钢制品具有包括氮改性的铬 - 基氧化物的表面层和在氮化期间形成的氮化铬的沉淀，其中表面层中的氧以比氮更高的浓度存在。 表面层还可以包括氮化钛和/或氧化铝的沉淀物。 处理过的制品中的表面层是化学不均匀的表面，而不是仅富含铬，钛或铝的均匀或半均匀的表面层。 通过氮化处理形成氮化钛和/或氧化铝的析出物，其中不锈钢中的钛和/或铝以表现出低接触电阻和良好耐腐蚀性的形式分离到表面层。