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公开(公告)号：US07821296B2
公开(公告)日：2010-10-26
申请号：US11498994
申请日：2006-08-04
IPC分类号： H03K19/094
CPC分类号： H03F1/0283 , H03F3/505 , H03F2200/24 , H03F2200/421 , H03F2200/453 , H03F2200/456 , H03F2203/5027 , H03F2203/5031 , H03F2203/5036
摘要： Two or more buffers may configured and arranged such that a quiescent current that flows through and biases a first buffer also flows through and biases a second buffer. The first and second buffers may, for example, be source followers used as reference buffers that drive inputs of a switched-capacitor circuit.
摘要翻译： 可以配置和布置两个或更多个缓冲器，使得流过并偏压第一缓冲器的静态电流也流过并偏压第二缓冲器。 第一和第二缓冲器可以例如是用作驱动开关电容器电路的输入的参考缓冲器的源极跟随器。
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公开(公告)号：US20090267639A1
公开(公告)日：2009-10-29
申请号：US12108873
申请日：2008-04-24
IPC分类号： H03K17/16
CPC分类号： H03K17/063 , H03F3/45179 , H03F2200/91 , H03F2203/45306 , H03F2203/45682 , H03H11/38 , H03H11/52
摘要： A system and method are provided for isolating an input without adding significant distortion and without significantly adversely affecting the bandwidth of input circuits. In one embodiment, a single ended signal is substantially cancelled by an arrangement including an input resistance path in parallel with a negative resistance path wherein both paths substantially match in resistance. In another embodiment, a differential signal is substantially cancelled by a pseudo differential arrangement including two independent input resistance paths each in parallel with a corresponding negative resistance path, wherein the resistance paths substantially match the input resistance paths. In yet another embodiment, a differential signal is substantially cancelled by a differential arrangement including two resistance paths wherein a first negative resistance path is coupled between the first differential input and the second differential output and the second negative resistance path is coupled between the second input and the first output. In yet another embodiment, a current controlled current source may provide the negative amplification for the negative resistance path.
摘要翻译： 提供了一种用于隔离输入而不增加显着失真并且不显着地不利地影响输入电路带宽的系统和方法。 在一个实施例中，单端信号基本上被包括与负电阻通路并联的输入电阻路径的装置抵消，其中两个路径基本上匹配电阻。 在另一个实施例中，差分信号基本上被包括两个独立输入电阻路径的伪差分布置消除，每个与对应的负电阻路径平行，其中电阻路径基本上与输入电阻路径匹配。 在另一个实施例中，差分信号基本上被包括两个电阻路径的差分布置消除，其中第一负电阻路径耦合在第一差分输入和第二差分输出之间，而第二负电阻路径耦合在第二输入和 第一个输出。 在另一个实施例中，电流控制电流源可以为负电阻路径提供负放大。
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公开(公告)号：US07602169B1
公开(公告)日：2009-10-13
申请号：US12108873
申请日：2008-04-24
IPC分类号： G01R1/20
CPC分类号： H03K17/063 , H03F3/45179 , H03F2200/91 , H03F2203/45306 , H03F2203/45682 , H03H11/38 , H03H11/52
摘要： A system and method are provided for isolating an input without adding significant distortion and without significantly adversely affecting the bandwidth of input circuits. In one embodiment, a single ended signal is substantially cancelled by an arrangement including an input resistance path in parallel with a negative resistance path wherein both paths substantially match in resistance. In another embodiment, a differential signal is substantially cancelled by a pseudo differential arrangement including two independent input resistance paths each in parallel with a corresponding negative resistance path, wherein the resistance paths substantially match the input resistance paths. In yet another embodiment, a differential signal is substantially cancelled by a differential arrangement including two resistance paths wherein a first negative resistance path is coupled between the first differential input and the second differential output and the second negative resistance path is coupled between the second input and the first output. In yet another embodiment, a current controlled current source may provide the negative amplification for the negative resistance path.
摘要翻译： 提供了一种用于隔离输入而不增加显着失真并且不显着地不利地影响输入电路带宽的系统和方法。 在一个实施例中，单端信号基本上被包括与负电阻通路并联的输入电阻路径的装置抵消，其中两个路径基本上匹配电阻。 在另一个实施例中，差分信号基本上被包括两个独立输入电阻路径的伪差分布置消除，每个与对应的负电阻路径平行，其中电阻路径基本上与输入电阻路径匹配。 在另一个实施例中，差分信号基本上被包括两个电阻路径的差分布置消除，其中第一负电阻路径耦合在第一差分输入和第二差分输出之间，而第二负电阻路径耦合在第二输入和 第一个输出。 在另一个实施例中，电流控制电流源可以为负电阻路径提供负放大。
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公开(公告)号：US06396429B2
公开(公告)日：2002-05-28
申请号：US09756306
申请日：2001-01-08
申请人： Lawrence A. Singer , Iuri Mehr
发明人： Lawrence A. Singer , Iuri Mehr
IPC分类号： H03M112
CPC分类号： H03M1/1245 , H03M1/167
摘要： An analog-to-digital converter including a quantizer and a residue generator, both of which sample an input voltage in parallel. The sampling characteristics of each of the residue generator and the quantizer are designed to substantially match one another. This converter may be used as a low-power ADC front-end circuit that does not require a dedicated sampleand-hold circuit. The front-end circuit consists of two substantially-matched sampling networks, one for the residue generator and the other for the quantizer, inside the first stage of the converter.
摘要翻译： 包括量化器和残留发生器的模数转换器，两者均并行地对输入电压进行采样。 每个残留发生器和量化器的采样特性被设计为基本上彼此匹配。 该转换器可以用作不需要专用采样和保持电路的低功耗ADC前端电路。 前端电路由转换器第一级内的两个基本匹配的采样网络组成，一个用于残留发生器，另一个用于量化器。
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5.发明授权
公开(公告)号：US5909131A
公开(公告)日：1999-06-01
申请号：US695823
申请日：1996-07-31
申请人： Lawrence A. Singer , Todd L. Brooks
发明人： Lawrence A. Singer , Todd L. Brooks
IPC分类号： G11C27/02
CPC分类号： G11C27/024
摘要： In a switched-capacitor input sampling structure, a resistor connected in series with the input structure, but after the output of the input switch limits the noise bandwidth of the input structure. The selected placement of the resistor does not appreciably limit the slewing or settling time of downstream circuit elements, resulting in a low noise bandwidth, high speed system.
摘要翻译： 在开关电容输入采样结构中，与输入结构串联的电阻器，但输入开关输出端限制输入结构的噪声带宽。 所选择的电阻放置不会明显限制下游电路元件的回转或稳定时间，导致低噪声带宽，高速系统。
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6.发明授权Method and apparatus for providing ESD/EOS protection for IC power supply pins 失效为IC电源引脚提供ESD / EOS保护的方法和设备
公开(公告)号：US5838146A
公开(公告)日：1998-11-17
申请号：US747217
申请日：1996-11-12
申请人： Lawrence A. Singer
发明人： Lawrence A. Singer
CPC分类号： H02H9/046
摘要： An apparatus and method for providing EOS/ESD protection against an EOS/ESD event across first and second pads of an integrated circuit. In one embodiment, the EOS/ESD protection circuit includes an NMOS device having a drain and source respectively coupled to the first and second pads of the integrated circuit, a capacitor coupled between the drain and gate of the NMOS device and a clamping circuit coupled between the gate and the source of the NMOS device to maintain a voltage at the gate less than or equal to a clamping voltage of the clamping circuit. In embodiments of the present invention, the protection circuit includes an active pull down circuit for reducing the voltage across the gate and source of the NMOS device to zero volts a predetermined period of time after the EOS/ESD event, and the protection circuit further includes a current source for providing bias current to the clamping circuit.
摘要翻译： 一种用于在集成电路的第一和第二焊盘上提供抵抗EOS / ESD事件的EOS / ESD保护的装置和方法。 在一个实施例中，EOS / ESD保护电路包括NMOS器件，其具有分别耦合到集成电路的第一和第二焊盘的漏极和源极，耦合在NMOS器件的漏极和栅极之间的电容器，以及耦合在 NMOS器件的栅极和源极以保持栅极处的电压小于或等于钳位电路的钳位电压。 在本发明的实施例中，保护电路包括有源下拉电路，用于在EOS / ESD事件之后的预定时间段内将NMOS器件的栅极和源极上的电压降低到零伏，并且保护电路还包括 用于向钳位电路提供偏置电流的电流源。
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公开(公告)号：US07920017B2
公开(公告)日：2011-04-05
申请号：US11305540
申请日：2005-12-16
CPC分类号： H02M3/073
摘要： A programmable clock booster system including a clock booster circuit including at least one boost capacitor connected between a first node and a second node for sampling an input voltage in a first phase and applying a boosting voltage to said second node during a second phase, and a programmable capacitor circuit connected to said first node for providing a programmable boosted voltage on said first node during said second phase.
摘要翻译： 一种可编程时钟升压器系统，包括时钟升压电路，其包括连接在第一节点和第二节点之间的至少一个升压电容器，用于对第一阶段中的输入电压进行采样，并且在第二阶段期间将升压电压施加到所述第二节点，以及 可编程电容器电路连接到所述第一节点，用于在所述第二阶段期间在所述第一节点上提供可编程升压电压。
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公开(公告)号：US06756842B2
公开(公告)日：2004-06-29
申请号：US10141191
申请日：2002-05-08
申请人： Iuri Mehr , Lawrence A. Singer , Wenhua Yang
发明人： Iuri Mehr , Lawrence A. Singer , Wenhua Yang
IPC分类号： H03F102
CPC分类号： H03F3/45762 , H03F3/005 , H03F3/45188 , H03F3/45632 , H03F2200/331 , H03F2203/45652
摘要： An a.c. coupled multistage high gain operational amplifier includes at least two gain stages, each having an input and an output; an a.c. coupling level shifting capacitance interconnecting the output of a first stage to the input of a second stage; and a charging circuit interconnecting with the a.c. coupling level shifting capacitance and the input of the second stage to charge the a.c. coupling level shifting capacitance in a track phase and to connect the a.c. coupling capacitance to the input of the second stage during a hold phase for dissociating the bias voltages of the stages.
摘要翻译： 一个 耦合多级高增益运算放大器包括至少两个增益级，每个具有输入和输出; 一个a.c. 将第一级的输出互连到第二级的输入的耦合电平移位电容; 和一个充电电路互相连接。 耦合电平移动电容和第二级的输入为a.c.充电。 耦合电平移位电容在轨道相位并连接a.c. 在用于解除级的偏置电压的保持阶段期间将电容耦合到第二级的输入。
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9.发明授权Latch structures and systems with enhanced speed and reduced current drain 有权锁存结构和系统具有增强的速度和减少的电流消耗公开(公告)号：US06556060B1
公开(公告)日：2003-04-29
申请号：US10166220
申请日：2002-06-06
IPC分类号： H03K3356
CPC分类号： H03K3/021 , H03K3/012 , H03K3/356104
摘要： Latch structures and systems are disclosed that enhance latch speed and reduce latch current drain while providing complementary metal-oxide-semiconductor (CMOS)-level latch signals. They are realized with bipolar junction structures and CMOS structures that are arranged to limit latch currents in response to CMOS-level sense signals Ssns.
摘要翻译： 公开了锁存结构和系统，其提供锁存速度并减少锁存电流漏极，同时提供互补的金属氧化物半导体（CMOS）级锁存信号。 它们被实现为双极结结构和CMOS结构，其被布置为响应于CMOS电平感测信号Ssns来限制锁存电流。
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公开(公告)号：US20080030233A1
公开(公告)日：2008-02-07
申请号：US11498994
申请日：2006-08-04
IPC分类号： H03K19/094
CPC分类号： H03F1/0283 , H03F3/505 , H03F2200/24 , H03F2200/421 , H03F2200/453 , H03F2200/456 , H03F2203/5027 , H03F2203/5031 , H03F2203/5036
摘要： Two or more buffers may configured and arranged such that a quiescent current that flows through and biases a first buffer also flows through and biases a second buffer. The first and second buffers may, for example, be source followers used as reference buffers that drive inputs of a switched-capacitor circuit.
摘要翻译： 可以配置和布置两个或更多个缓冲器，使得流过并偏压第一缓冲器的静态电流也流过并偏压第二缓冲器。 第一和第二缓冲器可以例如是用作驱动开关电容器电路的输入的参考缓冲器的源极跟随器。
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