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    Method of testing a semiconductor chip
    2.
    发明授权
    Method of testing a semiconductor chip 有权
    测试半导体芯片的方法

    公开(公告)号：US06720574B2

    公开(公告)日：2004-04-13

    申请号：US09986341

    申请日：2001-11-08

    申请人： Richard W. Arnold ,  Weldon Beardain ,  Daniel W. Prevedel ,  Donald E. Riley ,  Lester L. Wilson

    发明人： Richard W. Arnold ,  Weldon Beardain ,  Daniel W. Prevedel ,  Donald E. Riley ,  Lester L. Wilson

    IPC分类号： H01L2358

    CPC分类号： G01R1/0483 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0657 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4847 ,  H01L2224/49109 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06572 ,  H01L2225/06582 ,  H01L2225/06596 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/16195 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

    摘要： An apparatus for testing a semiconductor die and the method wherein there is provided a package having a cavity therein with a plurality of terminals in the package disposed at the periphery of the cavity. A semiconductor die to be tested and having a plurality of bond pads thereon is disposed in the cavity and an interconnecting layer having electrically conductive paths thereon is also disposed in the cavity, each of the paths having first and second spaced apart regions thereon, the first region of each path being aligned with and contacting a bond pad. An interconnection is provided between the second spaced apart region of each of the paths and one of the plurality of terminals. The second spaced apart region of each of the paths is preferably a bump aligned with and contacting one of the plurality of terminals. A compliant layer is preferably disposed over the interconnecting layer and provides a force causing engagement of at least the first spaced apart regions and the bond pads. The first region is preferably a compliant bump probe tip having a first predetermined height above the layer and includes a standoff on the layer having a second predetermined height above the layer less than the first height.

    摘要翻译： 一种用于测试半导体管芯的设备及其方法，其中提供了一种其中具有空腔的封装，该封装中的多个端子设置在空腔周边。 待测试并且在其上具有多个接合焊盘的半导体管芯设置在空腔中，并且其上具有导电路径的互连层也设置在空腔中，每个路径上具有第一和第二间隔开的区域，第一 每个路径的区域与接合焊盘对准并接触。 在每个路径的第二间隔开的区域和多个端子中的一个之间提供互连。 每个路径的第二间隔开的区域优选地是与多个端子之一对准并接触多个端子之一的凸块。 优选地，柔性层设置在互连层上方并且提供导致至少第一间隔开的区域和接合焊盘的接合的力。 第一区域优选地是具有在层上方的第一预定高度的柔顺凸起探针尖端，并且包括在该层上方的具有小于第一高度的第二预定高度的支座。

    Soft handling process tooling for low and medium volume known good die product
    3.
    发明授权
    Soft handling process tooling for low and medium volume known good die product 有权
    软处理工艺用于中低体积已知的好模具产品

    公开(公告)号：US06209532B1

    公开(公告)日：2001-04-03

    申请号：US09500519

    申请日：2000-02-09

    申请人： Richard W. Arnold ,  Lester L. Wilson

    发明人： Richard W. Arnold ,  Lester L. Wilson

    IPC分类号： B28D104

    CPC分类号： H01L21/6838 ,  B28D5/0082 ,  B28D5/0094 ,  H01L21/67144

    摘要： A method of transferring a semiconductor die from a wafer containing a plurality of semiconductor dice. There is provided a semiconductor wafer having a top side and an opposing bottom side and a plurality of dice formed therein, each die containing a portion of the top side and the opposing bottom side. The wafer is removably secured to a support and the wafer is operated upon to form individual dice on the support. The support is preferably a flexible film. A tool is disposed between the support and the bottom side of a the die by creating a vacuum between the tool and the bottom side to cause adherence of the die to the tool and the die is removed from the support with the tool and placed in a die carrier with the top side facing the carrier and the vacuum is then released. The film, when flexible, is stretched to separate the dice from each other and create streets between adjacent dice so that the tool can be disposed under the die from the street. The tool preferably includes an inclined surface with a port exiting at the surface extending through and out of the tool, the vacuum being created at the port and the inclined surface contacting the bottom side of the die. Prior to operation with the tool, a lifting member can impinge against the die bottom through the support to separate a portion of the die from the support, the tool entering beneath the die at the portion of the die removed from the support. The carrier preferably includes a carrier base having a plurality of vacuum ports and an air transmissive lint-free layer over the vacuum ports with the top side of the die abutting the lint-free layer, the die being disposed over one of the vacuum ports.

    摘要翻译： 从包含多个半导体晶片的晶片转移半导体管芯的方法。 提供了具有顶侧和相对的底侧以及形成在其中的多个骰子的半导体晶片，每个模包含顶侧和相对的底侧的一部分。 晶片可移除地固定到支撑件上，并且晶片被操作以在支撑件上形成单独的骰子。 该支撑体优选为柔性膜。 通过在工具和底侧之间产生真空，将模具设置在模具的支撑件和底侧之间，以使模具粘附到工具上，并且使用工具将模具从支撑件移除并放置在 模具载体，其顶侧面向载体，然后释放真空。 这种胶片在柔软的时候被拉伸，以将骰子彼此分离，并在相邻的骰子之间形成街道，以便该工具可以从街道上放置在模具下方。 该工具优选地包括倾斜表面，其中在表面处离开的端口延伸穿过和离开工具，在端口处产生真空，并且倾斜表面接触模具的底侧。 在使用该工具进行操作之前，提升构件可以通过支撑件撞击模具底部，以将模具的一部分与支撑件分离，该模具在模具的下方进入模具的从支撑件移除的部分。 载体优选地包括具有多个真空端口的载体基体和真空端口上的空气传输无绒层，其中模具的顶侧邻接无绒层，模具设置在真空端口之一上。

    Known good die using existing process infrastructure
    4.
    发明授权
    Known good die using existing process infrastructure 有权
    使用现有的流程基础设施已知很好

    公开(公告)号：US07898275B1

    公开(公告)日：2011-03-01

    申请号：US09164580

    申请日：1998-10-01

    申请人： Richard W. Arnold ,  Weldon Beardain ,  Daniel W. Prevedel ,  Donald E. Riley ,  Lester L. Wilson

    发明人： Richard W. Arnold ,  Weldon Beardain ,  Daniel W. Prevedel ,  Donald E. Riley ,  Lester L. Wilson

    IPC分类号： G01R31/00 ,  H01L23/48

    CPC分类号： G01R1/0483 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0657 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4847 ,  H01L2224/49109 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06572 ,  H01L2225/06582 ,  H01L2225/06596 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/16195 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

    摘要： An apparatus for testing a semiconductor die and the method wherein there is provided a package having a cavity therein with a plurality of terminals in the package disposed at the periphery of the cavity. A semiconductor die to be tested and having a plurality of bond pads thereon is disposed in the cavity and an interconnecting layer having electrically conductive paths thereon is also disposed in the cavity, each of the paths having first and second spaced apart regions thereon, the first region of each path being aligned with and contacting a bond pad. An interconnection is provided between the second spaced apart region of each of the paths and one of the plurality of terminals. The second spaced apart region of each of the paths is preferably a bump aligned with and contacting one of the plurality of terminals. A compliant layer is preferably disposed over the interconnecting layer and provides a force causing engagement of at least the first spaced apart regions and the bond pads. The first region is preferably a compliant bump probe tip having a first predetermined height above the layer and includes a standoff on the layer having a second predetermined height above the layer less than the first height.

    摘要翻译： 一种用于测试半导体管芯的设备及其方法，其中提供了一种其中具有空腔的封装，该封装中的多个端子设置在空腔周边。 待测试并且在其上具有多个接合焊盘的半导体管芯设置在空腔中，并且其上具有导电路径的互连层也设置在空腔中，每个路径上具有第一和第二间隔开的区域，第一 每个路径的区域与接合焊盘对准并接触。 在每个路径的第二间隔开的区域和多个端子中的一个之间提供互连。 每个路径的第二间隔开的区域优选地是与多个端子之一对准并接触多个端子之一的凸块。 优选地，柔性层设置在互连层上方并且提供导致至少第一间隔开的区域和接合焊盘的接合的力。 第一区域优选地是具有在层上方的第一预定高度的柔顺凸起探针尖端，并且包括在该层上方的具有小于第一高度的第二预定高度的支座。

    Digital signal processor/known good die packaging using rerouted existing package for test and burn-in carriers
    7.
    发明授权
    Digital signal processor/known good die packaging using rerouted existing package for test and burn-in carriers 有权
    数字信号处理器/已知的良好的芯片封装，使用重新布线的现有封装，用于测试和老化载体

    公开(公告)号：US06335226B1

    公开(公告)日：2002-01-01

    申请号：US09500507

    申请日：2000-02-09

    申请人： Richard W. Arnold ,  Lester L. Wilson ,  Mahmood A. Siddiqui ,  James A. Forster

    发明人： Richard W. Arnold ,  Lester L. Wilson ,  Mahmood A. Siddiqui ,  James A. Forster

    IPC分类号： H01L2130

    CPC分类号： G01R1/0483 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49109 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/15312 ,  H01L2924/00 ,  H01L2224/05599

    摘要： A package for a semiconductor die having a header with a cavity. The cavity includes a floor, sidewalls and a plurality of vertically spaced apart rows along the cavity sidewalls, each row including a plurality of spaced apart bond fingers. An electrically insulating membrane, preferably silicon, is disposed over the floor of the cavity, the membrane including a plurality of bumps, a plurality of peripherally located membrane bond pads and an interconnect from each of the bumps to a membrane bond pad. Bond wires are connected between the membrane bond pads and the bond fingers on the plurality of rows. A semiconductor die is provided having a plurality of bond pads, each bond pad contacting one of the bumps on the membrane. The header includes a plurality of alternating layers of electrically conducting material and electrically insulating material, the bond fingers on the header each being coupled to one of the layers of electrically conducting material. Each layer of electrically conducting material can include a plurality of spaced apart interconnect lines, each line coupled to one of the bond fingers. The package can include an electrical conductor interconnecting the electrically conducting material on spaced apart layers of the header.

    摘要翻译： 一种用于半导体管芯的封装，具有具有空腔的插头。 空腔包括沿着空腔侧壁的底板，侧壁和多个垂直间隔开的排，每排包括多个间隔开的接合指。 电绝缘膜（优选硅）设置在空腔的地板上，膜包括多个凸起，多个周边定位的膜接合焊盘和从每个凸块到膜接合焊盘的互连。 接合线连接在多个行上的膜接合焊盘和接合指状物之间。 提供具有多个接合焊盘的半导体管芯，每个接合焊盘接触膜上的凸块之一。 头部包括导电材料和电绝缘材料的多个交替层，每个头上的接合指状物连接到导电材料层之一。 每层导电材料可以包括多个间隔开的互连线，每条线耦合到一个键合指。 封装可以包括将导电材料互连在集管的间隔开的层上的电导体。