公开(公告)号：US06215168B1

公开(公告)日：2001-04-10

申请号：US09358625

申请日：1999-07-21

申请人： Linda Susan Brush ,  John Mannine Savidge Neilson

发明人： Linda Susan Brush ,  John Mannine Savidge Neilson

IPC分类号： H01L2358

CPC分类号： H01L29/0615 ,  H01L2924/0002 ,  H01L2924/00

摘要： A silicon semiconductor die comprises a heavily doped silicon substrate and an upper layer comprising doped silicon of a first conductivity type disposed on the substrate. The upper layer includes an active region that comprises a well region of a second, opposite conductivity type and an edge passivation zone comprising a junction termination extension (JTE) JTE region that includes portions extending away from and extending beneath the well region. The JTE region is of varying dopant density, the dopant density being maximum at a point substantially directly beneath the junction at the upper surface of the upper layer of the JTE region with the well region. The dopant density of the JTE region decreases in both lateral directions from its maximum point, becoming less in both the portions extending away from and beneath the well region.

摘要翻译： 硅半导体管芯包括重掺杂的硅衬底和设置在衬底上的包括第一导电类型的掺杂硅的上层。 上层包括有源区，其包括第二相反导电类型的阱区和包括连接终止延伸（JTE）JTE区的边缘钝化区，该区域包括在阱区域之外延伸并在其下延伸的部分。 JTE区域具有不同的掺杂剂密度，掺杂剂密度在基本上直接位于具有阱区域的JTE区域的上层的上表面的接合处的点处最大。 JTE区域的掺杂剂密度在两个横向方向上从其最大点减小，在两个延伸远离井下区域的部分中变小。

公开(公告)号：US6080614A

公开(公告)日：2000-06-27

申请号：US885877

申请日：1997-06-30

申请人： John Manning Sauidge Neilson ,  Linda Susan Brush ,  Frank Stensney ,  John Lawrence Benjamin ,  Anup Bhalla ,  Christopher Lawrence Rexer ,  Richard Douglas Stokes ,  Christopher Boguslow Kocon ,  Louise E. Skurkey ,  Christopher Michael Scarba

发明人： John Manning Sauidge Neilson ,  Linda Susan Brush ,  Frank Stensney ,  John Lawrence Benjamin ,  Anup Bhalla ,  Christopher Lawrence Rexer ,  Richard Douglas Stokes ,  Christopher Boguslow Kocon ,  Louise E. Skurkey ,  Christopher Michael Scarba

IPC分类号： H01L21/336 ,  H01L29/10 ,  H01L29/78 ,  H01L21/425 ,  H01L21/22 ,  H01L21/38

CPC分类号： H01L29/66712 ,  H01L29/1095 ,  H01L29/7802 ,  Y10S148/126

摘要： A method of fabricating a MOS-gated semiconductor device in which arsenic dopant is implanted through a mask to form a first layer, boron dopant is implanted through the mask to form a second layer deeper than the first layer, and in which a single diffusion step diffuses the implanted arsenic and the implanted boron at the same time to form a P+ body region with an N+ source region therein and a P type channel region.

摘要翻译： 一种制造MOS栅控半导体器件的方法，其中通过掩模注入砷掺杂剂以形成第一层，通过掩模注入硼掺杂剂以形成比第一层更深的第二层，并且其中单个扩散步骤 同时扩散注入的砷和注入的硼，以形成其中具有N +源极区的P +体区和P型沟道区。

公开(公告)号：US5877044A

公开(公告)日：1999-03-02

申请号：US814842

申请日：1997-03-11

申请人： John Manning Savidge Neilson ,  Christopher Boguslaw Kocon ,  Richard Douglas Stokes ,  Linda Susan Brush ,  John Lawrence Benjamin ,  Louise Ellen Skurkey ,  Christopher Lawrence Rexer

发明人： John Manning Savidge Neilson ,  Christopher Boguslaw Kocon ,  Richard Douglas Stokes ,  Linda Susan Brush ,  John Lawrence Benjamin ,  Louise Ellen Skurkey ,  Christopher Lawrence Rexer

IPC分类号： H01L29/78 ,  H01L21/331 ,  H01L21/336 ,  H01L29/06 ,  H01L29/10 ,  H01L21/332

CPC分类号： H01L29/66333 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/7802

摘要： A gate electrode control structure of an MOS-gated semiconductor device includes four doped regions including a first (source) region forming a first P-N junction with an enclosing composite region comprising a second, lightly doped (channel) region wholly enclosing a third heavily doped (body) region partly enclosing the first region, and a fourth (drain) region forming a P-N junction with the third region. The gate electrode control structure is fabricated using known gate electrode self-alignment doping processes but wherein, in the process for forming the third heavily doped region, a spacer layer is provided on the gate electrode for defining a spacing between the third region and the channel region with an improved degree of precision.

摘要翻译： MOS门控半导体器件的栅极电极控制结构包括四个掺杂区域，其包括形成第一PN结的第一（源极）区域，该第一PN结区域与封闭的复合区域包括完全包围第三重掺杂（沟道）区域的第二轻掺杂 部分地包围第一区域的第一（主体）区域和与第三区域形成PN结的第四（漏极）区域。 使用已知的栅电极自对准掺杂工艺制造栅电极控制结构，但是在用于形成第三重掺杂区的工艺中，在栅电极上设置间隔层，用于限定第三区与沟道之间的间隔 区域精度提高。