公开(公告)号：US5877044A

公开(公告)日：1999-03-02

申请号：US814842

申请日：1997-03-11

申请人： John Manning Savidge Neilson ,  Christopher Boguslaw Kocon ,  Richard Douglas Stokes ,  Linda Susan Brush ,  John Lawrence Benjamin ,  Louise Ellen Skurkey ,  Christopher Lawrence Rexer

发明人： John Manning Savidge Neilson ,  Christopher Boguslaw Kocon ,  Richard Douglas Stokes ,  Linda Susan Brush ,  John Lawrence Benjamin ,  Louise Ellen Skurkey ,  Christopher Lawrence Rexer

IPC分类号： H01L29/78 ,  H01L21/331 ,  H01L21/336 ,  H01L29/06 ,  H01L29/10 ,  H01L21/332

CPC分类号： H01L29/66333 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/7802

摘要： A gate electrode control structure of an MOS-gated semiconductor device includes four doped regions including a first (source) region forming a first P-N junction with an enclosing composite region comprising a second, lightly doped (channel) region wholly enclosing a third heavily doped (body) region partly enclosing the first region, and a fourth (drain) region forming a P-N junction with the third region. The gate electrode control structure is fabricated using known gate electrode self-alignment doping processes but wherein, in the process for forming the third heavily doped region, a spacer layer is provided on the gate electrode for defining a spacing between the third region and the channel region with an improved degree of precision.

摘要翻译： MOS门控半导体器件的栅极电极控制结构包括四个掺杂区域，其包括形成第一PN结的第一（源极）区域，该第一PN结区域与封闭的复合区域包括完全包围第三重掺杂（沟道）区域的第二轻掺杂 部分地包围第一区域的第一（主体）区域和与第三区域形成PN结的第四（漏极）区域。 使用已知的栅电极自对准掺杂工艺制造栅电极控制结构，但是在用于形成第三重掺杂区的工艺中，在栅电极上设置间隔层，用于限定第三区与沟道之间的间隔 区域精度提高。

公开(公告)号：US08294210B2

公开(公告)日：2012-10-23

申请号：US12815877

申请日：2010-06-15

申请人： Christopher Boguslaw Kocon ,  John Manning Savidge Neilson ,  Simon John Molloy ,  Haian Lin ,  Charles Walter Pearce ,  Gary Eugene Daum

发明人： Christopher Boguslaw Kocon ,  John Manning Savidge Neilson ,  Simon John Molloy ,  Haian Lin ,  Charles Walter Pearce ,  Gary Eugene Daum

IPC分类号： H01L29/66 ,  H01L21/336

CPC分类号： H01L29/861 ,  H01L29/402 ,  H01L29/6609 ,  H01L29/7835

摘要： A channel diode structure having a drift region and method of forming. A charge balanced channel diode structure having an electrode shield and method of forming.

摘要翻译： 具有漂移区域和形成方法的沟道二极管结构。 具有电极屏蔽的电荷平衡沟道二极管结构和形成方法。

公开(公告)号：US08288820B2

公开(公告)日：2012-10-16

申请号：US12815766

申请日：2010-06-15

申请人： Christopher Boguslaw Kocon ,  John Manning Savidge Neilson ,  Simon John Molloy ,  Haian Lin ,  Charles Walter Pearce

发明人： Christopher Boguslaw Kocon ,  John Manning Savidge Neilson ,  Simon John Molloy ,  Haian Lin ,  Charles Walter Pearce

IPC分类号： H01L29/66 ,  H01L21/336 ,  H01L25/00

CPC分类号： H01L29/7835 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/402 ,  H01L29/4175 ,  H01L29/41766 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7816

摘要： A high performance, power integrated circuit composed of two charge balanced, extended drain NMOS transistors (CBDEMOS) formed on an n-substrate. A CBDENMOS transistor with an n-type substrate source. A charge balanced channel diode (CBCD) with an n-type substrate. A process for forming a high performance, power integrated circuit composed of two CBDENMOS transistors formed on an n-substrate. A process for forming a power integrated circuit composed of one CBDENMOS transistor and one CBCD on an n-type substrate.

摘要翻译： 由n型衬底上形成的两个电荷平衡，扩展漏极NMOS晶体管（CBDEMOS）组成的高性能功率集成电路。 具有n型衬底源的CBDENMOS晶体管。 具有n型衬底的电荷平衡沟道二极管（CBCD）。 一种用于形成由在n衬底上形成的两个CBDENMOS晶体管组成的高性能功率集成电路的工艺。 一种在n型衬底上形成由一个CBDENMOS晶体管和一个CBCD组成的功率集成电路的工艺。

公开(公告)号：US20100315159A1

公开(公告)日：2010-12-16

申请号：US12815766

申请日：2010-06-15

申请人： Christopher Boguslaw Kocon ,  John Manning Savidge Neilson ,  Simon John Molloy ,  Haian Lin ,  Charles Walter Pearce

发明人： Christopher Boguslaw Kocon ,  John Manning Savidge Neilson ,  Simon John Molloy ,  Haian Lin ,  Charles Walter Pearce

IPC分类号： H01L25/00 ,  H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7835 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/402 ,  H01L29/4175 ,  H01L29/41766 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7816

摘要： A high performance, power integrated circuit composed of two charge balanced, extended drain NMOS transistors (CBDEMOS) formed on an n-substrate. A CBDENMOS transistor with an n-type substrate source. A charge balanced channel diode (CBCD) with an n-type substrate. A process for forming a high performance, power integrated circuit composed of two CBDENMOS transistors formed on an n-substrate. A process for forming a power integrated circuit composed of one CBDENMOS transistor and one CBCD on an n-type substrate.

摘要翻译： 由n型衬底上形成的两个电荷平衡，扩展漏极NMOS晶体管（CBDEMOS）组成的高性能功率集成电路。 具有n型衬底源的CBDENMOS晶体管。 具有n型衬底的电荷平衡沟道二极管（CBCD）。 一种用于形成由在n衬底上形成的两个CBDENMOS晶体管组成的高性能功率集成电路的工艺。 一种在n型衬底上形成由一个CBDENMOS晶体管和一个CBCD组成的功率集成电路的工艺。

公开(公告)号：US08680611B2

公开(公告)日：2014-03-25

申请号：US13600184

申请日：2012-08-30

申请人： Christopher Boguslaw Kocon ,  Steven Sapp ,  Paul Thorup ,  Dean Probst ,  Robert Herrick ,  Becky Losee ,  Hamza Yilmaz ,  Christopher Lawrence Rexer ,  Daniel Calafut

发明人： Christopher Boguslaw Kocon ,  Steven Sapp ,  Paul Thorup ,  Dean Probst ,  Robert Herrick ,  Becky Losee ,  Hamza Yilmaz ,  Christopher Lawrence Rexer ,  Daniel Calafut

IPC分类号： H01L29/76

CPC分类号： H01L29/7827 ,  H01L21/26586 ,  H01L27/0629 ,  H01L29/0619 ,  H01L29/0847 ,  H01L29/0869 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/66666 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7828 ,  H01L29/872 ,  H01L2924/13091

摘要： In accordance with an embodiment a structure can include a monolithically integrated trench field-effect transistor (FET) and Schottky diode. The structure can include a first gate trench extending into a semiconductor region, a second gate trench extending into the semiconductor region, and a source region flanking a side of the first gate trench. The source region can have a substantially triangular shape, and a contact opening extending into the semiconductor region between the first gate trench and the second gate trench. The structure can include a conductor layer disposed in the contact opening to electrically contact the source region along at least a portion of a slanted sidewall of the source region, and the semiconductor region along a bottom portion of the contact opening. The conductor layer can form a Schottky contact with the semiconductor region.

摘要翻译： 根据实施例，结构可以包括单片集成沟槽场效应晶体管（FET）和肖特基二极管。 该结构可以包括延伸到半导体区域的第一栅极沟槽，延伸到半导体区域中的第二栅极沟槽和在第一栅极沟槽的侧面的源极区域。 源极区域可以具有基本上三角形的形状，以及延伸到第一栅极沟槽和第二栅极沟槽之间的半导体区域中的接触开口。 该结构可以包括设置在接触开口中的导体层，以沿着源极区域的倾斜侧壁的至少一部分以及沿接触开口的底部部分的半导体区域电接触源极区域。 导体层可与半导体区形成肖特基接触。

公开(公告)号：US20120319197A1

公开(公告)日：2012-12-20

申请号：US13600184

申请日：2012-08-30

申请人： Christopher Boguslaw Kocon ,  Steven Sapp ,  Paul Thorup ,  Dean Probst ,  Robert Herrick ,  Becky Losee ,  Hamza Yilmaz ,  Christopher Lawrence Rexer ,  Daniel Calafut

发明人： Christopher Boguslaw Kocon ,  Steven Sapp ,  Paul Thorup ,  Dean Probst ,  Robert Herrick ,  Becky Losee ,  Hamza Yilmaz ,  Christopher Lawrence Rexer ,  Daniel Calafut

IPC分类号： H01L29/78

CPC分类号： H01L29/7827 ,  H01L21/26586 ,  H01L27/0629 ,  H01L29/0619 ,  H01L29/0847 ,  H01L29/0869 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/66666 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7828 ,  H01L29/872 ,  H01L2924/13091

摘要： In accordance with an embodiment a structure can include a monolithically integrated trench field-effect transistor (FET) and Schottky diode. The structure can include a first gate trench extending into a semiconductor region, a second gate trench extending into the semiconductor region, and a source region flanking a side of the first gate trench. The source region can have a substantially triangular shape, and a contact opening extending into the semiconductor region between the first gate trench and the second gate trench. The structure can include a conductor layer disposed in the contact opening to electrically contact the source region along at least a portion of a slanted sidewall of the source region, and the semiconductor region along a bottom portion of the contact opening. The conductor layer can form a Schottky contact with the semiconductor region.

摘要翻译： 根据实施例，结构可以包括单片集成沟槽场效应晶体管（FET）和肖特基二极管。 该结构可以包括延伸到半导体区域的第一栅极沟槽，延伸到半导体区域中的第二栅极沟槽和在第一栅极沟槽的侧面的源极区域。 源极区域可以具有基本上三角形的形状，以及延伸到第一栅极沟槽和第二栅极沟槽之间的半导体区域中的接触开口。 该结构可以包括设置在接触开口中的导体层，以沿着源极区域的倾斜侧壁的至少一部分以及沿接触开口的底部部分的半导体区域电接触源极区域。 导体层可与半导体区形成肖特基接触。

公开(公告)号：US20120156845A1

公开(公告)日：2012-06-21

申请号：US13325047

申请日：2011-12-13

申请人： Christopher Boguslaw Kocon ,  Steven Sapp ,  Paul Thorup ,  Dean Probst ,  Robert Herrick ,  Becky Losee ,  Hamza Yilmaz ,  Christopher Lawrence Rexer ,  Daniel Calafut

发明人： Christopher Boguslaw Kocon ,  Steven Sapp ,  Paul Thorup ,  Dean Probst ,  Robert Herrick ,  Becky Losee ,  Hamza Yilmaz ,  Christopher Lawrence Rexer ,  Daniel Calafut

IPC分类号： H01L21/336

CPC分类号： H01L29/7827 ,  H01L21/26586 ,  H01L27/0629 ,  H01L29/0619 ,  H01L29/0847 ,  H01L29/0869 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/66666 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7828 ,  H01L29/872 ,  H01L2924/13091

摘要： A method for forming a field effect transistor and Schottky diode includes forming a well region in a first portion of a silicon region where the field effect transistor is to be formed but not in a second portion of the silicon region where the Schottky diode is to be formed. Gate trenches are formed extending into the silicon region. A recessed gate is formed in each gate trench. A dielectric cap is formed over each recessed gate. Exposed surfaces of the well region are recessed to form a recess between every two adjacent trenches. Without masking any portion of the active area, a zero-degree blanket implant is performed to form a heavy body region of the second conductivity type in the well region between every two adjacent trenches.

摘要翻译： 用于形成场效应晶体管和肖特基二极管的方法包括在要形成场效应晶体管的硅区域的第一部分中形成阱区，但在肖特基二极管的硅区域的第二部分中不形成阱区 形成。 形成延伸到硅区域的栅极沟槽。 在每个栅极沟槽中形成凹陷栅极。 在每个凹入的栅极上形成电介质盖。 井区域的露出表面是凹进的，以在每两个相邻沟槽之间形成一个凹槽。 在不掩蔽有效区域的任何部分的情况下，执行零度覆盖植入以在每两个相邻沟槽之间的阱区域中形成第二导电类型的重体区域。

公开(公告)号：US20090111227A1

公开(公告)日：2009-04-30

申请号：US12346626

申请日：2008-12-30

申请人： Christopher Boguslaw Kocon ,  Steven Sapp ,  Paul Thorup ,  Dean Probst ,  Robert Herrick ,  Becky Losee ,  Hamza Yilmaz ,  Christopher Lawrence Rexer ,  Daniel Calafut

发明人： Christopher Boguslaw Kocon ,  Steven Sapp ,  Paul Thorup ,  Dean Probst ,  Robert Herrick ,  Becky Losee ,  Hamza Yilmaz ,  Christopher Lawrence Rexer ,  Daniel Calafut

IPC分类号： H01L21/336

CPC分类号： H01L29/7827 ,  H01L21/26586 ,  H01L27/0629 ,  H01L29/0619 ,  H01L29/0847 ,  H01L29/0869 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/66666 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7828 ,  H01L29/872 ,  H01L2924/13091

摘要： A method for forming a field effect transistor with an active area and a termination region surrounding the active area includes forming a well region in a first silicon region, where the well region and the first silicon region are of opposite conductivity type. Gate trenches extending through the well region and terminating within the first silicon region are formed. A recessed gate is formed in each gate trench. A dielectric cap is formed over each recessed gate. The well region is recessed between adjacent trenches to expose upper sidewalls of each dielectric cap. A blanket source implant is carried out to form a second silicon region in an upper portion of the recessed well region between every two adjacent trenches. A dielectric spacer is formed along each exposed upper sidewall of the dielectric cap, with every two adjacent dielectric spacers located between every two adjacent gate trenches forming an opening over the second silicon region. The second silicon region is recessed through the opening between every two adjacent dielectric spacers so that only portions of the second silicon region directly below the dielectric spacers remain. The remaining portions of the second silicon region form source regions.

摘要翻译： 用于形成具有有源区和围绕有源区的端接区的场效应晶体管的方法包括在阱区和第一硅区具有相反导电类型的第一硅区中形成阱区。 形成延伸穿过阱区并终止在第一硅区内的栅极沟槽。 在每个栅极沟槽中形成凹陷栅极。 在每个凹入的栅极上形成电介质盖。 阱区域在相邻沟槽之间凹陷以暴露每个电介质盖的上侧壁。 进行覆盖源植入以在每两个相邻沟槽之间的凹陷区域的上部中形成第二硅区域。 沿着电介质盖的每个暴露的上侧壁形成介电间隔物，每两个相邻的电介质间隔物位于每两个相邻栅极沟槽之间，形成在第二硅区上的开口。 第二硅区域在每两个相邻的电介质间隔物之间​​通过开口凹进，使得只有介电间隔物正下方的第二硅区域的部分保留。 第二硅区域的剩余部分形成源区域。

公开(公告)号：US20120133016A1

公开(公告)日：2012-05-31

申请号：US13365983

申请日：2012-02-03

申请人： Christopher Boguslaw Kocon

发明人： Christopher Boguslaw Kocon

IPC分类号： H01L29/872 ,  H01L21/329

CPC分类号： H01L29/407 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/41766 ,  H01L29/7816 ,  H01L29/7824

摘要： A schottky diode includes a drift region of a first conductivity type and a lightly doped silicon region of the first conductivity type in the drift region. A conductor layer is over and in contact with the lightly doped silicon region to form a schottky contact with the lightly doped silicon region. A highly doped silicon region of the first conductivity type is in the drift region and is laterally spaced from the lightly doped silicon region such that upon biasing the schottky diode in a conducting state, a current flows laterally between the lightly doped silicon region and the highly doped silicon region through the drift region. A plurality of trenches extend into the drift region perpendicular to the current flow. Each trench has a dielectric layer lining at least a portion of the trench sidewalls and at least one conductive electrode.

摘要翻译： 肖特基二极管包括漂移区中第一导电类型的漂移区和第一导电类型的轻掺杂硅区。 导体层与轻掺杂的硅区域结合并接触，以与轻掺杂的硅区域形成肖特基接触。 第一导电类型的高掺杂硅区域在漂移区域中并且与轻掺杂硅区域横向间隔开，使得在将肖特基二极管偏置在导通状态中时，电流在轻掺杂硅区域和高度掺杂的硅区域之间横向流动 掺杂硅区域通过漂移区域。 多个沟槽延伸到垂直于电流的漂移区域中。 每个沟槽具有内衬至少一部分沟槽侧壁和至少一个导电电极的电介质层。

公开(公告)号：US20110177662A1

公开(公告)日：2011-07-21

申请号：US13075091

申请日：2011-03-29

申请人： Hamza Yilmaz ,  Daniel Calafut ,  Christopher Boguslaw Kocon ,  Steven P. Sapp ,  Dean E. Probst ,  Nathan L. Kraft ,  Thomas E. Grebs ,  Rodney S. Ridley ,  Gary M. Dolny ,  Bruce D. Marchant ,  Joseph A. Yedinak

发明人： Hamza Yilmaz ,  Daniel Calafut ,  Christopher Boguslaw Kocon ,  Steven P. Sapp ,  Dean E. Probst ,  Nathan L. Kraft ,  Thomas E. Grebs ,  Rodney S. Ridley ,  Gary M. Dolny ,  Bruce D. Marchant ,  Joseph A. Yedinak

IPC分类号： H01L21/336

CPC分类号： H01L29/7827 ,  H01L21/26586 ,  H01L29/0878 ,  H01L29/402 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66666 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/872

摘要： A method of forming a field effect transistor includes: forming a trench in a semiconductor region; forming a shield electrode in the trench; performing an angled sidewall implant of impurities of the first conductivity type to form a channel enhancement region adjacent the trench; forming a body region of a second conductivity type in the semiconductor region; and forming a source region of the first conductivity type in the body region, the source region and an interface between the body region and the semiconductor region defining a channel region therebetween, the channel region extending along the trench sidewall. The channel enhancement region partially extends into a lower portion of the channel region to thereby reduce a resistance of the channel region.

摘要翻译： 形成场效应晶体管的方法包括：在半导体区域中形成沟槽; 在沟槽中形成屏蔽电极; 执行第一导电类型的杂质的成角度的侧壁注入，以形成与沟槽相邻的沟道增强区域; 在半导体区域中形成第二导电类型的体区; 并且在所述体区域中形成所述第一导电类型的源极区域，所述源极区域和所述体区域与所述半导体区域之间的界面在所述体区域中形成沟道区域，所述沟道区域沿着所述沟槽侧壁延伸。 沟道增强区域部分地延伸到沟道区的下部，从而减小沟道区的电阻。