公开(公告)号：US20140021628A1

公开(公告)日：2014-01-23

申请号：US13607555

申请日：2012-09-07

申请人： Yen-Hao Shih ,  Shih-Hung Chen ,  Teng-Hao Yeh ,  Chih-Wei Hu ,  Feng-Nien Tsai ,  Lo-Yueh Lin

发明人： Yen-Hao Shih ,  Shih-Hung Chen ,  Teng-Hao Yeh ,  Chih-Wei Hu ,  Feng-Nien Tsai ,  Lo-Yueh Lin

IPC分类号： H01L21/768 ,  H01L23/48

CPC分类号： H01L23/5226 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/32137 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76831 ,  H01L23/53271 ,  H01L23/5329 ,  H01L27/11526 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method is used with an IC device including a stack of dielectric/conductive layers to form interlayer connectors extending from a surface of the device to the conductive layers. Contact openings are created through a dielectric layer to a first conductive layer. N etch masks, with 2N−1 being less than W, 2N being greater than or equal to W, have spaced apart open etch regions and mask regions elsewhere. The stack of layers are etched only through W−1 contact openings to create extended contact openings extending to W−1 conductive layers; 2n−1 conductive layers are etched for up to half of the contact openings for each etch mask n=1, 2 . . . N. The contact openings are etched with different combinations of the etch masks' open etch regions. Interlayer connectors are formed in the contact openings.

摘要翻译： 一种使用IC器件的方法包括一叠介电/导电层，以形成从器件表面延伸到导电层的层间连接器。 通过电介质层产生接触开口到第一导电层。 N型蚀刻掩模，其中2N-1小于W，2N大于或等于W，其间具有间隔开的开放蚀刻区域和掩模区域。 层叠层仅通过W-1接触开口蚀刻以产生延伸到W-1导电层的延伸的接触开口; 对于每个蚀刻掩模n = 1,2，2n-1个导电层被蚀刻用于多达一半的接触开口。 。 。 用蚀刻掩模的开放蚀刻区域的不同组合蚀刻接触开口。 中间层连接器形成在接触开口中。

公开(公告)号：US08633099B1

公开(公告)日：2014-01-21

申请号：US13607555

申请日：2012-09-07

申请人： Yen-Hao Shih ,  Shih-Hung Chen ,  Teng-Hao Yeh ,  Chih-Wei Hu ,  Feng-Nien Tsai ,  Lo-Yueh Lin

发明人： Yen-Hao Shih ,  Shih-Hung Chen ,  Teng-Hao Yeh ,  Chih-Wei Hu ,  Feng-Nien Tsai ,  Lo-Yueh Lin

IPC分类号： H01L21/44 ,  H01L21/4763 ,  H01L23/48 ,  H01L29/40

CPC分类号： H01L23/5226 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/32137 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76831 ,  H01L23/53271 ,  H01L23/5329 ,  H01L27/11526 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method is used with an IC device including a stack of dielectric/conductive layers to form interlayer connectors extending from a surface of the device to the conductive layers. Contact openings are created through a dielectric layer to a first conductive layer. N etch masks, with 2N−1 being less than W, 2N being greater than or equal to W, have spaced apart open etch regions and mask regions elsewhere. The stack of layers are etched only through W−1 contact openings to create extended contact openings extending to W−1 conductive layers; 2n−1 conductive layers are etched for up to half of the contact openings for each etch mask n=1, 2 . . . N. The contact openings are etched with different combinations of the etch masks' open etch regions. Interlayer connectors are formed in the contact openings.

摘要翻译： 一种使用IC器件的方法包括一叠介电/导电层，以形成从器件表面延伸到导电层的层间连接。 通过电介质层产生接触开口到第一导电层。 N型蚀刻掩模，其中2N-1小于W，2N大于或等于W，其间具有间隔开的开放蚀刻区域和掩模区域。 层叠层仅通过W-1接触开口蚀刻以产生延伸到W-1导电层的延伸的接触开口; 对于每个蚀刻掩模n = 1,2，2n-1个导电层被蚀刻用于多达一半的接触开口。 。 。 用蚀刻掩模的开放蚀刻区域的不同组合蚀刻接触开口。 中间层连接器形成在接触开口中。

公开(公告)号：US20130075920A1

公开(公告)日：2013-03-28

申请号：US13240058

申请日：2011-09-22

申请人： Shih-Hung Chen ,  Yan-Ru Chen ,  Lo-Yueh Lin

发明人： Shih-Hung Chen ,  Yan-Ru Chen ,  Lo-Yueh Lin

IPC分类号： H01L23/48 ,  H01L21/283

CPC分类号： G11C5/04 ,  G11C5/06 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76831 ,  H01L27/0688 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11575 ,  H01L27/11582

摘要： An IC device comprises a stack of contact levels, each including conductive layer and an insulation layer. A dielectric liner surrounds an interlevel conductor within an opening in the stack of contact levels. The opening passes through a portion of the stack of contact levels. The interlevel conductor is electrically insulated from the conductive layers of each of the contact levels through the dielectric liner. A portion of the conductive layer at the opening is recessed relative to adjacent insulation layers. The dielectric liner may have portions extending between adjacent insulation layers.

摘要翻译： IC器件包括一叠接触电平，每一层包括导电层和绝缘层。 电介质衬垫围绕接触层叠层内的开口内的层间导体。 开口穿过一叠接触层的一部分。 层间导体与通过电介质衬垫的每个接触层的导电层电绝缘。 开口处的导电层的一部分相对于相邻的绝缘层凹陷。 电介质衬垫可以具有在相邻绝缘层之间延伸的部分。

公开(公告)号：US08558319B2

公开(公告)日：2013-10-15

申请号：US13172449

申请日：2011-06-29

申请人： Lo-Yueh Lin

发明人： Lo-Yueh Lin

IPC分类号： H01L21/70

CPC分类号： H01L29/7881 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/66825

摘要： A semiconductor memory device includes a substrate and a plurality of rows of memory cells. The substrate comprises a plurality of isolation structures and a plurality of active regions. Each of the active regions is spaced apart from another active region by one of the isolation structures. In a cross-section of the substrate between two rows of memory cells in a direction parallel to the two rows of memory cells, a maximum height of each isolation structure with respect to a bottom of the substrate is lower than or equal to minimum heights of active regions adjacent thereto.

摘要翻译： 半导体存储器件包括衬底和多行存储单元。 衬底包括多个隔离结构和多个有源区。 每个有源区域通过隔离结构之一与另一有源区域间隔开。 在平行于两排存储单元的方向上的两行存储单元之间的衬底的横截面中，每个隔离结构相对于衬底底部的最大高度低于或等于 与其相邻的活性区。

公开(公告)号：US20130001669A1

公开(公告)日：2013-01-03

申请号：US13172449

申请日：2011-06-29

申请人： Lo-Yueh Lin

发明人： Lo-Yueh Lin

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L29/7881 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/66825

摘要： A semiconductor memory device includes a substrate and a plurality of rows of memory cells. The substrate comprises a plurality of isolation structures and a plurality of active regions. Each of the active regions is spaced apart from another active region by one of the isolation structures. In a cross-section of the substrate between two rows of memory cells in a direction parallel to the two rows of memory cells, a maximum height of each isolation structure with respect to a bottom of the substrate is lower than or equal to minimum heights of active regions adjacent thereto.

摘要翻译： 半导体存储器件包括衬底和多行存储单元。 衬底包括多个隔离结构和多个有源区。 每个有源区域通过隔离结构之一与另一有源区域间隔开。 在平行于两排存储单元的方向上的两行存储单元之间的衬底的横截面中，每个隔离结构相对于衬底底部的最大高度低于或等于 与其相邻的活性区。

公开(公告)号：US08541882B2

公开(公告)日：2013-09-24

申请号：US13240058

申请日：2011-09-22

申请人： Shih-Hung Chen ,  Yan-Ru Chen ,  Lo-Yueh Lin

发明人： Shih-Hung Chen ,  Yan-Ru Chen ,  Lo-Yueh Lin

IPC分类号： H01L23/48 ,  H01L21/283

CPC分类号： G11C5/04 ,  G11C5/06 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76831 ,  H01L27/0688 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11575 ,  H01L27/11582

摘要： An IC device comprises a stack of contact levels, each including conductive layer and an insulation layer. A dielectric liner surrounds an interlevel conductor within an opening in the stack of contact levels. The opening passes through a portion of the stack of contact levels. The interlevel conductor is electrically insulated from the conductive layers of each of the contact levels through the dielectric liner. A portion of the conductive layer at the opening is recessed relative to adjacent insulation layers. The dielectric liner may have portions extending between adjacent insulation layers.

摘要翻译： IC器件包括一叠接触电平，每一层包括导电层和绝缘层。 电介质衬垫围绕接触层叠层内的开口内的层间导体。 开口穿过一叠接触层的一部分。 层间导体与通过电介质衬垫的每个接触层的导电层电绝缘。 开口处的导电层的一部分相对于相邻的绝缘层凹入。 电介质衬垫可以具有在相邻绝缘层之间延伸的部分。