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12 条记录 (耗时 0.019 秒)

    Stacked IC device with recessed conductive layers adjacent to interlevel conductors
    1.
    发明授权
    Stacked IC device with recessed conductive layers adjacent to interlevel conductors 有权
    具有与层间导体相邻的凹陷导电层的堆叠IC器件

    公开(公告)号：US08541882B2

    公开(公告)日：2013-09-24

    申请号：US13240058

    申请日：2011-09-22

    申请人： Shih-Hung Chen ,  Yan-Ru Chen ,  Lo-Yueh Lin

    发明人： Shih-Hung Chen ,  Yan-Ru Chen ,  Lo-Yueh Lin

    IPC分类号： H01L23/48 ,  H01L21/283

    CPC分类号： G11C5/04 ,  G11C5/06 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76831 ,  H01L27/0688 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11575 ,  H01L27/11582

    摘要： An IC device comprises a stack of contact levels, each including conductive layer and an insulation layer. A dielectric liner surrounds an interlevel conductor within an opening in the stack of contact levels. The opening passes through a portion of the stack of contact levels. The interlevel conductor is electrically insulated from the conductive layers of each of the contact levels through the dielectric liner. A portion of the conductive layer at the opening is recessed relative to adjacent insulation layers. The dielectric liner may have portions extending between adjacent insulation layers.

    摘要翻译： IC器件包括一叠接触电平，每一层包括导电层和绝缘层。 电介质衬垫围绕接触层叠层内的开口内的层间导体。 开口穿过一叠接触层的一部分。 层间导体与通过电介质衬垫的每个接触层的导电层电绝缘。 开口处的导电层的一部分相对于相邻的绝缘层凹入。 电介质衬垫可以具有在相邻绝缘层之间延伸的部分。

    Multilayer Connection Structure and Making Method
    2.
    发明申请
    Multilayer Connection Structure and Making Method 有权
    多层连接结构与制作方法

    公开(公告)号：US20130075920A1

    公开(公告)日：2013-03-28

    申请号：US13240058

    申请日：2011-09-22

    申请人： Shih-Hung Chen ,  Yan-Ru Chen ,  Lo-Yueh Lin

    发明人： Shih-Hung Chen ,  Yan-Ru Chen ,  Lo-Yueh Lin

    IPC分类号： H01L23/48 ,  H01L21/283

    CPC分类号： G11C5/04 ,  G11C5/06 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76831 ,  H01L27/0688 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11575 ,  H01L27/11582

    摘要： An IC device comprises a stack of contact levels, each including conductive layer and an insulation layer. A dielectric liner surrounds an interlevel conductor within an opening in the stack of contact levels. The opening passes through a portion of the stack of contact levels. The interlevel conductor is electrically insulated from the conductive layers of each of the contact levels through the dielectric liner. A portion of the conductive layer at the opening is recessed relative to adjacent insulation layers. The dielectric liner may have portions extending between adjacent insulation layers.

    摘要翻译： IC器件包括一叠接触电平，每一层包括导电层和绝缘层。 电介质衬垫围绕接触层叠层内的开口内的层间导体。 开口穿过一叠接触层的一部分。 层间导体与通过电介质衬垫的每个接触层的导电层电绝缘。 开口处的导电层的一部分相对于相邻的绝缘层凹陷。 电介质衬垫可以具有在相邻绝缘层之间延伸的部分。

    THREE DIMENSIONAL GATE STRUCTURES WITH HORIZONTAL EXTENSIONS
    5.
    发明申请
    THREE DIMENSIONAL GATE STRUCTURES WITH HORIZONTAL EXTENSIONS 有权
    三维门结构与水平扩展

    公开(公告)号：US20140140131A1

    公开(公告)日：2014-05-22

    申请号：US13681133

    申请日：2012-11-19

    申请人： Teng-Hao Yeh ,  Yen-Hao Shih ,  Yan-Ru Chen

    发明人： Teng-Hao Yeh ,  Yen-Hao Shih ,  Yan-Ru Chen

    IPC分类号： H01L29/788 ,  G11C5/06 ,  G11C16/04 ,  H01L21/28

    CPC分类号： G11C5/06 ,  G11C5/063 ,  G11C16/0483 ,  G11C2213/71 ,  H01L21/28282 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/7926

    摘要： A device on an integrated circuit includes a stack of alternating semiconductor lines and insulating lines, and a gate structure over the stack of semiconductor lines. The gate structure includes a vertical portion adjacent the stack on the at least one side, and horizontal extension portions between the semiconductor lines. Sides of the insulating lines can be recessed relative to sides of the semiconductor lines, so at least one side of the stack includes recesses between semiconductor lines. The horizontal extension portions can be in the recesses. The horizontal extension portions have inside surfaces adjacent the sides of the insulating lines, and outside surfaces that can be flush with the sides of the semiconductor lines. The device may include a second gate structure spaced away from the first mentioned gate structure, and an insulating element between horizontal extension portions of the second gate structure and the first mentioned gate structure.

    摘要翻译： 集成电路中的器件包括交替的半导体线路和绝缘线路的堆叠以及在半导体线路堆叠上的栅极结构。 栅极结构包括在至少一个侧面上与堆叠相邻的垂直部分和半导体线之间的水平延伸部分。 绝缘线的边可以相对于半导体线的侧面凹陷，因此堆叠的至少一侧包括半导体线之间的凹槽。 水平延伸部分可以在凹槽中。 水平延伸部具有与绝缘线的侧面相邻的内表面以及可与半导体线的侧面齐平的外表面。 器件可以包括与第一提到的栅极结构间隔开的第二栅极结构，以及在第二栅极结构的水平延伸部分和第一个提到的栅极结构之间的绝缘元件。

    Three dimensional gate structures with horizontal extensions
    9.
    发明授权
    Three dimensional gate structures with horizontal extensions 有权
    具有水平延伸的三维门结构

    公开(公告)号：US09196315B2

    公开(公告)日：2015-11-24

    申请号：US13681133

    申请日：2012-11-19

    申请人： Teng-Hao Yeh ,  Yen-Hao Shih ,  Yan-Ru Chen

    发明人： Teng-Hao Yeh ,  Yen-Hao Shih ,  Yan-Ru Chen

    IPC分类号： G11C11/34 ,  G11C5/06 ,  H01L21/28 ,  H01L29/792 ,  H01L27/115 ,  G11C16/04

    CPC分类号： G11C5/06 ,  G11C5/063 ,  G11C16/0483 ,  G11C2213/71 ,  H01L21/28282 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/7926

    摘要： A device on an integrated circuit includes a stack of alternating semiconductor lines and insulating lines, and a gate structure over the stack of semiconductor lines. The gate structure includes a vertical portion adjacent the stack on the at least one side, and horizontal extension portions between the semiconductor lines. Sides of the insulating lines can be recessed relative to sides of the semiconductor lines, so at least one side of the stack includes recesses between semiconductor lines. The horizontal extension portions can be in the recesses. The horizontal extension portions have inside surfaces adjacent the sides of the insulating lines, and outside surfaces that can be flush with the sides of the semiconductor lines. The device may include a second gate structure spaced away from the first mentioned gate structure, and an insulating element between horizontal extension portions of the second gate structure and the first mentioned gate structure.

    摘要翻译： 集成电路中的器件包括交替的半导体线路和绝缘线路的堆叠以及在半导体线路堆叠上的栅极结构。 栅极结构包括在至少一个侧面上与堆叠相邻的垂直部分和半导体线之间的水平延伸部分。 绝缘线的边可以相对于半导体线的侧面凹陷，因此堆叠的至少一侧包括半导体线之间的凹槽。 水平延伸部分可以在凹槽中。 水平延伸部具有与绝缘线的侧面相邻的内表面以及可与半导体线的侧面齐平的外表面。 器件可以包括与第一提到的栅极结构间隔开的第二栅极结构，以及在第二栅极结构的水平延伸部分和第一个提到的栅极结构之间的绝缘元件。

    Verification algorithm for metal-oxide resistive memory
    10.
    发明授权
    Verification algorithm for metal-oxide resistive memory 有权
    金属氧化物电阻记忆体验证算法

    公开(公告)号：US08699258B2

    公开(公告)日：2014-04-15

    申请号：US13212493

    申请日：2011-08-18

    申请人： Wei-Chih Chien ,  Ming-Hsiu Lee ,  Yan-Ru Chen

    发明人： Wei-Chih Chien ,  Ming-Hsiu Lee ,  Yan-Ru Chen

    IPC分类号： G11C11/00

    CPC分类号： G11C7/1045 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/0064 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/0073 ,  G11C2013/0092 ,  G11C2213/79

    摘要： Memory devices and methods for operating such devices are described which can effectively program the metal-oxide memory elements in an array, while also avoiding applying unnecessarily high voltage pulses. Programming operations described herein include applying a lower voltage pulse across a metal-oxide memory element to establish a desired resistance state, and only applying a higher voltage pulse when the lower voltage pulse is insufficient to program the memory element. In doing so, issues associated with applying unnecessarily high voltages across the memory element can be avoided.

    摘要翻译： 描述了用于操作这种装置的存储器件和方法，其可以有效地将阵列中的金属氧化物存储元件编程，同时还避免施加不必要的高电压脉冲。 本文描述的编程操作包括在金属氧化物存储元件上施加较低电压脉冲以建立期望的电阻状态，并且仅当较低电压脉冲不足以对存储元件进行编程时才施加较高电压脉冲。 在这样做时，可以避免与在存储元件上施加不必要的高电压有关的问题。