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    Timing closure methodology including placement with initial delay values
    1.
    发明授权
    Timing closure methodology including placement with initial delay values 有权
    定时关闭方法，包括具有初始延迟值的位置

    公开(公告)号：US08621403B2

    公开(公告)日：2013-12-31

    申请号：US10828547

    申请日：2004-04-19

    申请人： Lukas P. P. P. van Ginneken ,  Prabhakar Kudva

    发明人： Lukas P. P. P. van Ginneken ,  Prabhakar Kudva

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5072 ,  G06F17/505 ,  G06F17/5068

    摘要： An automated method for designing an integrated circuit layout using a computer based upon an electronic circuit description and based upon cells which are selected from a cell library, each of the cells having an associated area, comprising the steps of: (a) placing each of the cells in the integrated circuit layout so that the cells can be coupled together by wires to form a circuit path having an associated predetermined delay constraint wherein the cells are coupled together based upon the electronic circuit description input to the computer; (b) connecting the cells together with the wires to form the circuit path; and (c) adjusting an area of at least one of the cells to satisfy the associated predetermined delay constraint of the circuit path.

    摘要翻译： 一种用于基于电子电路描述使用计算机设计集成电路布局的自动化方法，并且基于从单元库中选择的单元，其中每个单元具有相关联的区域，包括以下步骤：（a）将每个 集成电路布局中的单元，使得单元可以通过导线耦合在一起以形成具有相关联的预定延迟约束的电路路径，其中基于输入到计算机的电子电路描述将单元耦合在一起; （b）将电池与电线连接以形成电路路径; 以及（c）调整所述单元中的至少一个的区域以满足所述电路路径的相关联的预定延迟约束。

    Timing optimization in presence of interconnect delays
    3.
    发明授权
    Timing optimization in presence of interconnect delays 有权
    存在互连延迟的定时优化

    公开(公告)号：US06553338B1

    公开(公告)日：2003-04-22

    申请号：US09300557

    申请日：1999-04-27

    申请人： Premal V. Buch ,  Hamid Savoj ,  Lukas P. P. P. Van Ginneken

    发明人： Premal V. Buch ,  Hamid Savoj ,  Lukas P. P. P. Van Ginneken

    IPC分类号： G06F1750

    CPC分类号： G06F17/505 ,  G06F17/5022

    摘要： A strategy for optimal buffering in the case of an infinitely long wire buffered with an arbitrary number of equally spaced single-size buffers is presented. A simple but efficient technique is proposed using this to choose a buffer size and determine a good inter-buffering distance up front, thus enabling fast, efficient buffer insertion. The analysis also allows representing delays of long wires as a simple function of the length and buffer and wire widths. Based on this, a novel constant wire delay approach is proposed where the proposed wire delay model is used for fairly accurate prediction of wire delays early in the design process and these predictions are later met via buffer insertion and wire sizing.

    摘要翻译： 提出了在任意数量的等间距单个缓冲器中缓冲的无限长的线的情况下的优化缓冲策略。 提出了一种简单而有效的技术，用于选择缓冲区大小，并确定前面的良好的缓冲间距离，从而实现快速，高效的缓冲区插入。 该分析还允许将长线的延迟表示为长度和缓冲器和线宽的简单函数。 基于此，提出了一种新颖的恒定线延迟方法，其中提出的线延迟模型用于在设计过程的早期对线延迟进行相当准确的预测，并且这些预测稍后通过缓冲器插入和线尺寸来满足。

    Timing closure methodology
    4.
    发明授权
    Timing closure methodology 失效

    公开(公告)号：US06453446B1

    公开(公告)日：2002-09-17

    申请号：US09054379

    申请日：1998-04-02

    申请人： Lukas P. P. P. van Ginneken

    发明人： Lukas P. P. P. van Ginneken

    IPC分类号： G06F1750

    CPC分类号： G06F17/5072 ,  G06F17/505 ,  G06F17/5068

    摘要： An automated method for designing an integrated circuit layout using a computer based upon an electronic circuit description and based upon cells which are selected from a cell library, each of the cells having an associated area, comprising the steps of: (a) placing each of the cells in the integrated circuit layout so that the cells can be coupled together by wires to form a circuit path having an associated predetermined delay constraint wherein the cells are coupled together based upon the electronic circuit description input to the computer; (b) connecting the cells together with the wires to form the circuit path; and (c) adjusting an area of at least one of the cells to satisfy the associated predetermined delay constraint of the circuit path.

    Method of designing a constraint-driven integrated circuit layout
    5.
    发明授权
    Method of designing a constraint-driven integrated circuit layout 失效
    设计约束驱动集成电路布局的方法

    公开(公告)号：US06230304B1

    公开(公告)日：2001-05-08

    申请号：US09054319

    申请日：1998-04-02

    申请人： Patrick R. Groeneveld ,  Lukas P. P. P. van Ginneken

    发明人： Patrick R. Groeneveld ,  Lukas P. P. P. van Ginneken

    IPC分类号： G06F1750

    CPC分类号： G06F17/505 ,  G06F17/5068 ,  G06F17/5072 ,  G06F17/5077

    摘要： An automated method for designing an integrated circuit layout with a computer, based upon an electronic circuit description and upon a selected plurality of cells from a cell library, comprising the steps of: (a) assigning each of the cells to one of a plurality of buckets designated on the integrated circuit layout, each of the cells being connected to one of the other cells; (b) performing global routing to connect at least some of the selected cells of step (a) together such that global routes are formed to provide net topology information; (c) performing track routing which sets the position of each of the global routes; (d) performing detailed placement such that the positions of all selected cells are fixed within each of the buckets designated on the integrated circuit layout; and (e) performing detailed routing such that detailed routes are formed to complete the integrated circuit layout.

    摘要翻译： 一种用于基于电子电路描述和来自单元库的所选择的多个单元从计算机设计集成电路布局的自动化方法，包括以下步骤：（a）将每个单元分配给多个单元中的一个， 在集成电路布局上指定的桶，每个单元连接到其他单元之一; （b）执行全局路由以将步骤（a）的所选择的小区中的至少一些连接在一起，使得形成全局路由以提供网络拓扑信息; （c）执行设置每个全局路线的位置的轨道路由; （d）执行详细的放置，使得所选择的单元的位置固定在集成电路布局上指定的每个桶内; 和（e）执行详细路由，使得形成详细的路由以完成集成电路布局。

    Timing closure methodology
    6.
    发明授权
    Timing closure methodology 无效
    时序关闭方法

    公开(公告)号：US06725438B2

    公开(公告)日：2004-04-20

    申请号：US10134076

    申请日：2002-04-24

    申请人： Lukas P. P. P. van Ginneken

    发明人： Lukas P. P. P. van Ginneken

    IPC分类号： G06F1750

    CPC分类号： G06F17/5072 ,  G06F17/505 ,  G06F17/5068

    摘要： An automated method for designing an integrated circuit layout using a computer based upon an electronic circuit description and based upon cells which are selected from a cell library, each of the cells having an associated area, comprising the steps of: (a) placing each of the cells in the integrated circuit layout so that the cells can be coupled together by wires to form a circuit path having an associated predetermined delay constraint wherein the cells are coupled together based upon the electronic circuit description input to the computer; (b) connecting the cells together with the wires to form the circuit path; and (c) adjusting an area of at least one of the cells to satisfy the associated predetermined delay constraint of the circuit path.

    摘要翻译： 一种用于基于电子电路描述使用计算机设计集成电路布局的自动化方法，并且基于从单元库中选择的单元，其中每个单元具有相关联的区域，包括以下步骤：（a）将每个 集成电路布局中的单元，使得单元可以通过导线耦合在一起以形成具有相关联的预定延迟约束的电路路径，其中基于输入到计算机的电子电路描述将单元耦合在一起; （b）将电池与电线连接以形成电路路径; 以及（c）调整所述单元中的至少一个的区域以满足所述电路路径的相关联的预定延迟约束。

    Automated design of parallel drive standard cells
    7.
    发明授权
    Automated design of parallel drive standard cells 有权
    并行驱动器标准单元的自动设计

    公开(公告)号：US06496965B1

    公开(公告)日：2002-12-17

    申请号：US09399986

    申请日：1999-09-20

    申请人： Lukas P. P. P. van Ginneken ,  Raymond X. T. Nijssen ,  Premal Buch

    发明人： Lukas P. P. P. van Ginneken ,  Raymond X. T. Nijssen ,  Premal Buch

    IPC分类号： G06F1750

    CPC分类号： G06F17/505

    摘要： Methods and apparatuses for automated design of parallel drive standard cells are disclosed. The capacitive load to be driven by a particular output of a standard cell is determined. The driving capacity of the output is also determined. Based on the capacitive load to be driven and the driving capacity, a number of standard cells to be used is determined. The multiple standard cells are coupled in parallel having the respective outputs coupled to the capacitive load to be driven. In one embodiment, the standard cells coupled is parallel are placed such that the connection between the respective outputs and the load are substantially equal.

    摘要翻译： 公开了用于并行驱动器标准单元的自动设计的方法和装置。 确定由标准单元的特定输出驱动的电容性负载。 输出的驱动能力也被确定。 基于要驱动的容性负载和驱动能力，确定要使用的多个标准单元。 多个标准单元并联耦合，其中各个输出耦合到待驱动的电容负载。 在一个实施例中，耦合的标准单元是平行的，使得各个输出和负载之间的连接基本相等。

    Incremental timing analysis
    8.
    发明授权
    Incremental timing analysis 失效
    增量时序分析

    公开(公告)号：US5508937A

    公开(公告)日：1996-04-16

    申请号：US49699

    申请日：1993-04-16

    申请人： Richard P. Abato ,  Anthony D. Drumm ,  David J. Hathaway ,  Lukas P. P. P. van Ginneken

    发明人： Richard P. Abato ,  Anthony D. Drumm ,  David J. Hathaway ,  Lukas P. P. P. van Ginneken

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5031

    摘要： Incremental timing analyzer for selectively performing timing analysis on a revised electronic circuit design resulting from one or more modifications to an initial electronic circuit design having input nodes, output nodes, and active elements electrically connected therebetween in a set of signal paths interconnected by a plurality of nodes. Each signal path has a timing delay associated therewith. Data is recorded representative of the modification's affect on relative timing values for a set of signals propagated through the circuit design. The recorded data includes a leftmost frontier of change in relative timing values and a rightmost frontier of change in relative timing values. Upon presentation of a specific timing analysis request, incremental timing analysis on the selected portion of the modified electronic circuit design is conducted employing the recorded frontiers of change to limit the timing value analysis. The concepts presented may be used for incremental recalculation of any signal value propagated forward or backward through a logic network.

    摘要翻译： 增量定时分析器，用于选择性地对经修改的电子电路设计进行定时分析，所述修正的电子电路设计是由具有输入节点，输出节点和电连接在其间的有源元件的初始电子电路设计的一个或多个修改而导致的， 节点。 每个信号路径具有与之相关的定时延迟。 记录数据表示修改对通过电路设计传播的一组信号的相对定时值的影响。 所记录的数据包括相对定时值变化的最左边界和相对定时值的最右边改变的边界。 在呈现特定的时间分析请求时，利用所记录的改变的边界进行修改的电子电路设计的所选部分的增量定时分析，以限制时序值分析。 所呈现的概念可用于对通过逻辑网络向前或向后传播的任何信号值的增量重新计算。