Method to suppress subthreshold leakage due to sharp isolation corners
in submicron FET structures
    1.
    发明授权
    Method to suppress subthreshold leakage due to sharp isolation corners in submicron FET structures 失效
    抑制由亚微米FET结构中的尖锐隔离角引起的亚阈值泄漏的方法

    公开(公告)号:US6144081A

    公开(公告)日:2000-11-07

    申请号:US540961

    申请日:1995-10-11

    摘要: A field effect transistor (FET) device, which mitigates leakage current induced along the edges of the FET device, is isolated by shallow trench isolation having a channel width between a first and a second shallow trench at a first and second shallow trench edges. A gate extends across the channel width between the first and second shallow trenches. The gate has a first length at the shallow trench edges and a second length less than the first length between the shallow trench edges. The first length and the second length are related such that the threshold voltage, V.sub.t, at the shallow trench edges is substantially equal to V.sub.t between the shallow trench edges. The gate structure of the FET device is produced using a unique phase shift mask that allows the manufacture of submicron FET devices with very small channel lengths.

    摘要翻译: 通过在第一和第二浅沟槽边缘处具有第一和第二浅沟槽之间的沟道宽度的浅沟槽隔离来隔离减轻沿着FET器件边缘感应的漏电流的场效应晶体管(FET)器件。 栅极延伸穿过第一和第二浅沟槽之间的沟道宽度。 栅极在浅沟槽边缘处具有第一长度,并且具有小于浅沟槽边缘之间的第一长度的第二长度。 第一长度和第二长度相关联,使得浅沟槽边缘处的阈值电压Vt基本上等于浅沟槽边缘之间的Vt。 FET器件的栅极结构使用独特的相移掩模产生,其允许制造具有非常小的沟道长度的亚微米FET器件。