公开(公告)号：US6144081A

公开(公告)日：2000-11-07

申请号：US540961

申请日：1995-10-11

申请人： Louis Lu-Chen Hsu ,  Chang-Ming Hsieh ,  Lyndon Ronald Logan ,  Jack Allan Mandelman ,  Seiki Ogura

发明人： Louis Lu-Chen Hsu ,  Chang-Ming Hsieh ,  Lyndon Ronald Logan ,  Jack Allan Mandelman ,  Seiki Ogura

IPC分类号： G03F1/08 ,  H01L21/027 ,  H01L21/28 ,  H01L21/336 ,  H01L21/76 ,  H01L29/423 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L29/66575 ,  H01L21/28123 ,  H01L29/4238 ,  H01L29/7831

摘要： A field effect transistor (FET) device, which mitigates leakage current induced along the edges of the FET device, is isolated by shallow trench isolation having a channel width between a first and a second shallow trench at a first and second shallow trench edges. A gate extends across the channel width between the first and second shallow trenches. The gate has a first length at the shallow trench edges and a second length less than the first length between the shallow trench edges. The first length and the second length are related such that the threshold voltage, V.sub.t, at the shallow trench edges is substantially equal to V.sub.t between the shallow trench edges. The gate structure of the FET device is produced using a unique phase shift mask that allows the manufacture of submicron FET devices with very small channel lengths.

摘要翻译： 通过在第一和第二浅沟槽边缘处具有第一和第二浅沟槽之间的沟道宽度的浅沟槽隔离来隔离减轻沿着FET器件边缘感应的漏电流的场效应晶体管（FET）器件。 栅极延伸穿过第一和第二浅沟槽之间的沟道宽度。 栅极在浅沟槽边缘处具有第一长度，并且具有小于浅沟槽边缘之间的第一长度的第二长度。 第一长度和第二长度相关联，使得浅沟槽边缘处的阈值电压Vt基本上等于浅沟槽边缘之间的Vt。 FET器件的栅极结构使用独特的相移掩模产生，其允许制造具有非常小的沟道长度的亚微米FET器件。

公开(公告)号：US6107141A

公开(公告)日：2000-08-22

申请号：US163151

申请日：1998-09-29

申请人： Louis Lu-Chen Hsu ,  Chang-Ming Hsieh ,  Seiki Ogura

发明人： Louis Lu-Chen Hsu ,  Chang-Ming Hsieh ,  Seiki Ogura

IPC分类号： G11C17/00 ,  G11C16/04 ,  G11C16/06 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L29/66825 ,  G11C16/0425 ,  H01L21/2815 ,  H01L27/115 ,  H01L29/42328 ,  H01L29/7885

摘要： An EEPROM cell includes a dual-gate transistor having a floating gate for storing the data and a select gate to access the cell, the two gates each being formed from poly sidewalls and being separated by a thin vertical oxide member that is formed by growing oxide on the vertical poly sidewalls of an aperture in which the select gate is formed, so that the final structure has dimensions that are less than those obtainable with optical lithography because both gates are sidewalls and therefore not limited to the dimensions achievable with optical lithography.

摘要翻译： EEPROM单元包括具有用于存储数据的浮动栅极和访问单元的选择栅极的双栅极晶体管，每个栅极均由多边形成，并由通过生长氧化物形成的薄垂直氧化物元件分隔开 在其中形成选择栅极的孔径的垂直多边形上，使得最终结构的尺寸小于通过光学光刻获得的尺寸，因为两个栅极都是侧壁，因此不限于光学光刻实现的尺寸。

公开(公告)号：US5910912A

公开(公告)日：1999-06-08

申请号：US968736

申请日：1992-10-30

申请人： Louis Lu-Chen Hsu ,  Chang-Ming Hsieh ,  Seiki Ogura

发明人： Louis Lu-Chen Hsu ,  Chang-Ming Hsieh ,  Seiki Ogura

IPC分类号： G11C17/00 ,  G11C16/04 ,  G11C16/06 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L29/66825 ,  G11C16/0425 ,  H01L21/2815 ,  H01L27/115 ,  H01L29/42328 ,  H01L29/7885

摘要： An EEPROM cell includes a dual-gate transistor having a floating gate for storing the data and a select gate to access the cell, the two gates each being formed from poly sidewalls and being separated by a thin vertical oxide member that is formed by growing oxide on the vertical poly sidewalls of an aperture in which the select gate is formed, so that the final structure has dimensions that are less than those obtainable with optical lithography because both gates are sidewalls and therefore not limited to the dimensions achievable with optical lithography.

摘要翻译： EEPROM单元包括具有用于存储数据的浮动栅极和访问单元的选择栅极的双栅极晶体管，每个栅极均由多边形成，并由通过生长氧化物形成的薄垂直氧化物元件分隔开 在其中形成选择栅极的孔径的垂直多边形上，使得最终结构的尺寸小于通过光学光刻获得的尺寸，因为两个栅极都是侧壁，因此不限于光学光刻实现的尺寸。

公开(公告)号：US5729039A

公开(公告)日：1998-03-17

申请号：US642834

申请日：1996-05-03

申请人： Klaus Dietrich Beyer ,  Taqi Nasser Buti ,  Chang-Ming Hsieh ,  Louis Lu-Chen Hsu

发明人： Klaus Dietrich Beyer ,  Taqi Nasser Buti ,  Chang-Ming Hsieh ,  Louis Lu-Chen Hsu

IPC分类号： H01L21/336 ,  H01L29/786 ,  H01L27/12

CPC分类号： H01L29/66772 ,  H01L29/41783 ,  H01L29/78612 ,  Y10S148/15

摘要： An SOI transistor has a self-aligned body contact formed through an extension to the gate, thereby forming the body contact with minimal increase in area and also avoiding the need to tie the source to the body, as in prior art schemes that passed the body contact through the source. The body contact aperture is formed by raising the source and drain to define an initial aperture, depositing a conformal layer that is etched to create aperture-defining sidewalls and etching the contact aperture using these sidewalls to define sidewall support members that support insulating sidewalls to isolate the collection electrode from both the gate and from the source and drain.

摘要翻译： SOI晶体管具有通过到门的延伸形成的自对准体接触，从而以最小的面积增加形成身体接触，并且还避免了将源连接到身体的需要，如通过身体的现有技术方案 通过来源联系。 身体接触孔通过提高源极和漏极以形成初始孔径而形成，沉积被蚀刻以形成孔限定侧壁的共形层并且使用这些侧壁蚀刻接触孔以限定支撑绝缘侧壁以隔离的侧壁支撑构件 收集电极来自闸门和源极和漏极。

公开(公告)号：US5721144A

公开(公告)日：1998-02-24

申请号：US547180

申请日：1995-10-24

申请人： Chang-Ming Hsieh ,  Somnuk Ratanaphanyarat ,  Shao-Fu Sanford Chu ,  Louis Lu-chen Hsu

发明人： Chang-Ming Hsieh ,  Somnuk Ratanaphanyarat ,  Shao-Fu Sanford Chu ,  Louis Lu-chen Hsu

IPC分类号： H01L21/8234 ,  H01L27/02 ,  H01L27/088

CPC分类号： H01L21/823475 ,  H01L21/823425 ,  H01L27/0203 ,  H01L27/088 ,  Y10S148/055

摘要： An improved design for high aspect ratio MOS devices is capable of 100% yields. The design is suitable for low voltage CMOS devices, such as microprocessors, which use the high aspect ratio MOS devices in embedded applications, and for HEMTs in high frequency applications, such as high power microwave devices. The high yields reduce manufacturing costs. A modular MOS concept is introduced to realize the 100% yield of large channel width devices. The structure of the modular MOS device is a regular MOS device with a unit device channel width. This can be a multi-finger device which has a proper dimension to be able to fit in a given layout area. Therefore, the number of modules which are needed to form a full large width device is not only determined by module size, but also on the manufacturing yield record, allowed chip real estate and performance requirement.

摘要翻译： 高纵横比MOS器件的改进设计能够获得100％的产量。 该设计适用于诸如微处理器的低电压CMOS器件，其使用嵌入式应用中的高纵横比MOS器件，以及用于诸如高功率微波器件的高频应用中的HEMT。 高产量降低了制造成本。 引入模块化MOS概念，实现大通道宽度器件的100％产量。 模块化MOS器件的结构是具有单位器件沟道宽度的常规MOS器件。 这可以是具有适当尺寸以能够适应给定布局区域的多指装置。 因此，形成全宽度器件所需的模块数量不仅取决于模块尺寸，还取决于制造产量记录，芯片的可用性和性能要求。

公开(公告)号：US5962895A

公开(公告)日：1999-10-05

申请号：US336956

申请日：1994-11-10

申请人： Klaus Dietrich Beyer ,  Taqi Nasser Buti ,  Chang-Ming Hsieh ,  Louis Lu-Chen Hsu

发明人： Klaus Dietrich Beyer ,  Taqi Nasser Buti ,  Chang-Ming Hsieh ,  Louis Lu-Chen Hsu

IPC分类号： H01L21/336 ,  H01L29/786 ,  H01L27/01

CPC分类号： H01L29/66772 ,  H01L29/41783 ,  H01L29/78612 ,  Y10S148/15

摘要： SOI Transistor Having a Self-aligned Body Contact An SOI transistor has a self-aligned body contact formed through an extension to the gate, thereby forming the body contact with minimal increase in area and also avoiding the need to tie the source to the body, as in prior art schemes that passed the body contact through the source. The body contact aperture is formed by raising the source and drain to define an initial aperture, depositing a conformal layer that is etched to create aperture-defining sidewalls and etching the contact aperture using these sidewalls to define sidewall support members that support insulating sidewalls to isolate the collection electrode from both the gate and from the source and drain.

摘要翻译： 具有自对准体接触的SOI晶体管SOI晶体管具有通过到门的延伸形成的自对准体接触，从而以最小的面积增加形成身体接触，并且还避免将源与身体相关联， 如通过身体接触通过源的现有技术方案中那样。 身体接触孔通过提高源极和漏极以形成初始孔径而形成，沉积被蚀刻以形成孔限定侧壁的共形层并且使用这些侧壁蚀刻接触孔以限定支撑绝缘侧壁以隔离的侧壁支撑构件 收集电极来自闸门和源极和漏极。

公开(公告)号：US5874764A

公开(公告)日：1999-02-23

申请号：US685792

申请日：1996-07-24

申请人： Chang-Ming Hsieh ,  Somnuk Ratanaphanyarat ,  Shao-Fu Sanford Chu ,  Louis Lu-chen Hsu

发明人： Chang-Ming Hsieh ,  Somnuk Ratanaphanyarat ,  Shao-Fu Sanford Chu ,  Louis Lu-chen Hsu

IPC分类号： H01L21/8234 ,  H01L27/02 ,  H01L27/088 ,  H01L27/118

CPC分类号： H01L21/823475 ,  H01L21/823425 ,  H01L27/0203 ,  H01L27/088 ,  Y10S148/055

摘要： An improved design for high aspect ratio MOS devices is capable of 100% yields. The design is suitable for low voltage CMOS devices, such as microprocessors, which use the high aspect ratio MOS devices in embedded applications, and for HEMTs in high frequency applications, such as high power microwave devices. The high yields reduce manufacturing costs. A modular MOS concept is introduced to realize the 100% yield of large channel width devices. The structure of the modular MOS device is a regular MOS device with a unit device channel width. This can be a multi-finger device which has a proper dimension to be able to fit in a given layout area. Therefore, the number of modules which are needed to form a full large width device is not only determined by module size, but also on the manufacturing yield record, allowed chip real estate and performance requirement.

摘要翻译： 高纵横比MOS器件的改进设计能够获得100％的产量。 该设计适用于诸如微处理器的低电压CMOS器件，其使用嵌入式应用中的高纵横比MOS器件，以及用于诸如高功率微波器件的高频应用中的HEMT。 高产量降低了制造成本。 引入模块化MOS概念，实现大通道宽度器件的100％产量。 模块化MOS器件的结构是具有单位器件沟道宽度的常规MOS器件。 这可以是具有适当尺寸以能够适应给定布局区域的多指装置。 因此，形成全宽度器件所需的模块数量不仅取决于模块尺寸，还取决于制造产量记录，芯片的可用性和性能要求。

公开(公告)号：US5389559A

公开(公告)日：1995-02-14

申请号：US161763

申请日：1993-12-02

申请人： Chang-Ming Hsieh ,  Louis L. Hsu ,  Toshio Mii ,  Seiki Ogura ,  Joseph F. Shepard

发明人： Chang-Ming Hsieh ,  Louis L. Hsu ,  Toshio Mii ,  Seiki Ogura ,  Joseph F. Shepard

IPC分类号： H01L21/8242 ,  H01L27/108 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L27/10861 ,  H01L27/10829

摘要： A trench capacitor DRAM cell with Shallow Trench Isolation (STI), a self-aligned buried strap and the method of making the cell. A trench capacitor is defined in a substrate. The trench capacitor's polysilicon (poly) plate is recessed below the surface of the substrate and the trench sidewalls are exposed above the poly. A doped poly layer is deposited over the surface contacting both the sidewall and the trench capacitor's poly plate. Horizontal portions of the poly layer are removed either through chemmech polishing or Reactive Ion Etching (RIE). A shallow trench is formed, removing one formerly exposed trench sidewall and a portion of the trench capacitor's poly plate in order to isolate the DRAM cell from adjacent cells. The remaining poly strap, along the trench sidewall contacting the poly plate, is self aligned to contact the source of the DRAM Pass gate Field Effect Transistor (FET). After the shallow trench is filled with oxide, FET's are formed on the substrate, completing the cell. In an alternate embodiment, instead of recessing the poly plate, a shallow trench is formed spanning the entire width of the trench capacitor. The deposited polysilicon is selectively removed, having straps that strap the poly plate to the shallow trench sidewall.

摘要翻译： 具有浅沟槽隔离（STI）的沟槽电容器DRAM单元，自对准掩埋带和制造电池的方法。 沟槽电容器限定在衬底中。 沟槽电容器的多晶硅（poly）板在衬底的表面下方凹入，并且沟槽侧壁暴露在聚合物上方。 在与侧壁和沟槽电容器的多晶硅板接触的表面上沉积掺杂的多晶硅层。 通过化学抛光或反应离子蚀刻（RIE）去除多层的水平部分。 形成浅沟槽，去除一个以前暴露的沟槽侧壁和沟槽电容器的多晶片的一部分，以便将DRAM单元与相邻单元隔离。 沿着与多晶硅板接触的沟槽侧壁的剩余多晶带自对准以接触DRAM通过栅极场效应晶体管（FET）的源极。 在浅沟槽充满氧化物之后，在衬底上形成FET，从而完成电池。 在替代实施例中，代替凹陷多晶硅，形成跨越沟槽电容器的整个宽度的浅沟槽。 选择性地去除沉积的多晶硅，具有将多晶板绑定到浅沟槽侧壁的带。

公开(公告)号：US5528062A

公开(公告)日：1996-06-18

申请号：US900041

申请日：1992-06-17

申请人： Chang-Ming Hsieh ,  Louis L. C. Hsu ,  Seiki Ogura

发明人： Chang-Ming Hsieh ,  Louis L. C. Hsu ,  Seiki Ogura

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L27/10829 ,  H01L27/10823

摘要： A high density, DRAM cell array with a very short channel, vertical gate transfer transistor that can be manufactured using conventional photolithography process steps. The conventional four-by-four DRAM array shown schematically in FIG. 1a is rearranged to the shared-gate, double-bit array shown schematically in FIG. 1b. Trench storage capacitors and vertical FET transistors are arranged in pairs with a common vertical gate and a common substrate, allowing both bit and substrate contacts to be shared by adjacent cells.

摘要翻译： 具有非常短的通道的高密度DRAM单元阵列，垂直栅极转移晶体管可以使用常规光刻工艺步骤制造。 图1中示意性示出的常规四乘四DRAM阵列。 1a被重新布置到图1中示意性示出的共享门双位阵列。 1b。 沟槽存储电容器和垂直FET晶体管与公共垂直栅极和公共衬底成对配置，允许位和衬底触点由相邻单元共享。

公开(公告)号：US5340759A

公开(公告)日：1994-08-23

申请号：US113941

申请日：1993-08-30

申请人： Chang-Ming Hsieh ,  Louis L. C. Hsu ,  Seiki Ogura

发明人： Chang-Ming Hsieh ,  Louis L. C. Hsu ,  Seiki Ogura

IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L27/12 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L29/78642 ,  H01L27/1203

摘要： A field effect transistor (FET) with a vertical gate and a very thin channel sandwiched between source and drain layers. In a preferred embodiment of the invention, the FET is formed on a silicon on insulator (SOI) substrate with the silicon layer serving as the first layer (e.g., the source layer). A low temperature epitaxial (LTE) process is used to form a very thin (e.g., 0.1 .mu.m) channel, and a chemically vapor deposited polysilicon layer forms the top layer (e.g., the drain layer). An opening is etched through the three layers to the insulator substrate and its wall is oxidized, forming a gate oxide. Polysilicon is deposited to fill the opening and form the vertical gate.

摘要翻译： 具有垂直栅极和夹在源极和漏极层之间的非常薄的沟道的场效应晶体管（FET）。 在本发明的一个优选实施例中，FET在硅绝缘体（SOI）衬底上形成，硅层用作第一层（例如，源层）。 使用低温外延（LTE）工艺来形成非常薄（例如0.1μm）的通道，并且化学气相沉积的多晶硅层形成顶层（例如，漏层）。 通过三层蚀刻开口到绝缘体衬底，并且其壁被氧化，形成栅极氧化物。 沉积多晶硅以填充开口并形成垂直浇口。