公开(公告)号：US6144081A

公开(公告)日：2000-11-07

申请号：US540961

申请日：1995-10-11

申请人： Louis Lu-Chen Hsu ,  Chang-Ming Hsieh ,  Lyndon Ronald Logan ,  Jack Allan Mandelman ,  Seiki Ogura

发明人： Louis Lu-Chen Hsu ,  Chang-Ming Hsieh ,  Lyndon Ronald Logan ,  Jack Allan Mandelman ,  Seiki Ogura

IPC分类号： G03F1/08 ,  H01L21/027 ,  H01L21/28 ,  H01L21/336 ,  H01L21/76 ,  H01L29/423 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L29/66575 ,  H01L21/28123 ,  H01L29/4238 ,  H01L29/7831

摘要： A field effect transistor (FET) device, which mitigates leakage current induced along the edges of the FET device, is isolated by shallow trench isolation having a channel width between a first and a second shallow trench at a first and second shallow trench edges. A gate extends across the channel width between the first and second shallow trenches. The gate has a first length at the shallow trench edges and a second length less than the first length between the shallow trench edges. The first length and the second length are related such that the threshold voltage, V.sub.t, at the shallow trench edges is substantially equal to V.sub.t between the shallow trench edges. The gate structure of the FET device is produced using a unique phase shift mask that allows the manufacture of submicron FET devices with very small channel lengths.

摘要翻译： 通过在第一和第二浅沟槽边缘处具有第一和第二浅沟槽之间的沟道宽度的浅沟槽隔离来隔离减轻沿着FET器件边缘感应的漏电流的场效应晶体管（FET）器件。 栅极延伸穿过第一和第二浅沟槽之间的沟道宽度。 栅极在浅沟槽边缘处具有第一长度，并且具有小于浅沟槽边缘之间的第一长度的第二长度。 第一长度和第二长度相关联，使得浅沟槽边缘处的阈值电压Vt基本上等于浅沟槽边缘之间的Vt。 FET器件的栅极结构使用独特的相移掩模产生，其允许制造具有非常小的沟道长度的亚微米FET器件。

公开(公告)号：US6107141A

公开(公告)日：2000-08-22

申请号：US163151

申请日：1998-09-29

申请人： Louis Lu-Chen Hsu ,  Chang-Ming Hsieh ,  Seiki Ogura

发明人： Louis Lu-Chen Hsu ,  Chang-Ming Hsieh ,  Seiki Ogura

IPC分类号： G11C17/00 ,  G11C16/04 ,  G11C16/06 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L29/66825 ,  G11C16/0425 ,  H01L21/2815 ,  H01L27/115 ,  H01L29/42328 ,  H01L29/7885

摘要： An EEPROM cell includes a dual-gate transistor having a floating gate for storing the data and a select gate to access the cell, the two gates each being formed from poly sidewalls and being separated by a thin vertical oxide member that is formed by growing oxide on the vertical poly sidewalls of an aperture in which the select gate is formed, so that the final structure has dimensions that are less than those obtainable with optical lithography because both gates are sidewalls and therefore not limited to the dimensions achievable with optical lithography.

摘要翻译： EEPROM单元包括具有用于存储数据的浮动栅极和访问单元的选择栅极的双栅极晶体管，每个栅极均由多边形成，并由通过生长氧化物形成的薄垂直氧化物元件分隔开 在其中形成选择栅极的孔径的垂直多边形上，使得最终结构的尺寸小于通过光学光刻获得的尺寸，因为两个栅极都是侧壁，因此不限于光学光刻实现的尺寸。

公开(公告)号：US5910912A

公开(公告)日：1999-06-08

申请号：US968736

申请日：1992-10-30

申请人： Louis Lu-Chen Hsu ,  Chang-Ming Hsieh ,  Seiki Ogura

发明人： Louis Lu-Chen Hsu ,  Chang-Ming Hsieh ,  Seiki Ogura

IPC分类号： G11C17/00 ,  G11C16/04 ,  G11C16/06 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L29/66825 ,  G11C16/0425 ,  H01L21/2815 ,  H01L27/115 ,  H01L29/42328 ,  H01L29/7885

摘要： An EEPROM cell includes a dual-gate transistor having a floating gate for storing the data and a select gate to access the cell, the two gates each being formed from poly sidewalls and being separated by a thin vertical oxide member that is formed by growing oxide on the vertical poly sidewalls of an aperture in which the select gate is formed, so that the final structure has dimensions that are less than those obtainable with optical lithography because both gates are sidewalls and therefore not limited to the dimensions achievable with optical lithography.

摘要翻译： EEPROM单元包括具有用于存储数据的浮动栅极和访问单元的选择栅极的双栅极晶体管，每个栅极均由多边形成，并由通过生长氧化物形成的薄垂直氧化物元件分隔开 在其中形成选择栅极的孔径的垂直多边形上，使得最终结构的尺寸小于通过光学光刻获得的尺寸，因为两个栅极都是侧壁，因此不限于光学光刻实现的尺寸。

公开(公告)号：US5892257A

公开(公告)日：1999-04-06

申请号：US708432

申请日：1996-09-05

申请人： Joyce Elizabeth Acocella ,  Carol Galli ,  Louis Lu-Chen Hsu ,  Seiki Ogura ,  Nivo Rovedo ,  Joseph Francis Shepard

发明人： Joyce Elizabeth Acocella ,  Carol Galli ,  Louis Lu-Chen Hsu ,  Seiki Ogura ,  Nivo Rovedo ,  Joseph Francis Shepard

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11526 ,  H01L27/115 ,  H01L27/11546 ,  Y10S148/117 ,  Y10S438/981

摘要： Improved packing density as well as improved performance and manufacturing yield is achieved in an electrically programmable memory by confining floating gate structures between isolation structures covered with a thin nitride layer. The confinement of the floating gate is achieved by planarization, preferably with a self-limiting chemical/mechanical polishing process, to the surface of the nitride layer covering the isolation structures. Gate oxide and control electrode connections can then be formed on a substantially planar surface without compromising the quality of the gate oxide or breakdown voltage the device must withstand for programming. Since severe topology is avoided over which these connections are formed, improved formation of low resistance connections, possibly including metal connections, are possible and allow scaling of transistors of the memory cells to be scaled to sizes not previously possible.

摘要翻译： 通过将浮置栅极结构限制在被薄氮化物层覆盖的隔离结构之间，可在电可编程存储器中实现提高的封装密度以及改进的性能和制造产量。 浮栅的限制是通过平面化，优选采用自限制化学/机械抛光工艺，覆盖覆盖隔离结构的氮化物层的表面来实现的。 然后可以在基本平坦的表面上形成栅极氧化物和控制电极连接，而不会损害器件必须承受编程的栅极氧化物的质量或击穿电压。 由于避免了形成这些连接的严格的拓扑结构，所以可能包括可能包括金属连接的低电阻连接的形成得到改进，并且允许将存储器单元的晶体管缩放到先前不可能的尺寸。

公开(公告)号：US5643813A

公开(公告)日：1997-07-01

申请号：US434698

申请日：1995-05-04

申请人： Joyce Elizabeth Acocella ,  Carol Galli ,  Louis Lu-Chen Hsu ,  Seiki Ogura ,  Nivo Rovedo ,  Joseph Francis Shepard

发明人： Joyce Elizabeth Acocella ,  Carol Galli ,  Louis Lu-Chen Hsu ,  Seiki Ogura ,  Nivo Rovedo ,  Joseph Francis Shepard

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11526 ,  H01L27/115 ,  H01L27/11546 ,  Y10S148/117 ,  Y10S438/981

摘要： Improved packing density as well as improved performance and manufacturing yield is achieved in an electrically programmable memory by confining floating gate structures between isolation structures covered with a thin nitride layer. The confinement of the floating gate is achieved by planarization, preferably with a self-limiting chemical/mechanical polishing process, to the surface of the nitride layer covering the isolation structures. Gate oxide and control electrode connections can then be formed on a substantially planar surface without compromising the quality of the gate oxide or breakdown voltage the device must withstand for programming. Since severe topology is avoided over which these connections are formed, improved formation of low resistance connections, possibly including metal connections, are possible and allow scaling of transistors of the memory cells to be scaled to sizes not previously possible.

摘要翻译： 通过将浮置栅极结构限制在被薄氮化物层覆盖的隔离结构之间，可在电可编程存储器中实现提高的封装密度以及改进的性能和制造产量。 浮栅的限制是通过平面化，优选采用自限制化学/机械抛光工艺，覆盖覆盖隔离结构的氮化物层的表面来实现的。 然后可以在基本平坦的表面上形成栅极氧化物和控制电极连接，而不会损害器件必须承受编程的栅极氧化物的质量或击穿电压。 由于避免了形成这些连接的严格的拓扑结构，所以可能包括可能包括金属连接的低电阻连接的形成得到改进，并且允许将存储器单元的晶体管缩放到先前不可能的尺寸。

公开(公告)号：US5622881A

公开(公告)日：1997-04-22

申请号：US319393

申请日：1994-10-06

申请人： Joyce E. Acocella ,  Carol Galli ,  Louis Lu-Chen Hsu ,  Seiki Ogura ,  Nivo Rovedo ,  Joseph F. Shepard

发明人： Joyce E. Acocella ,  Carol Galli ,  Louis Lu-Chen Hsu ,  Seiki Ogura ,  Nivo Rovedo ,  Joseph F. Shepard

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C13/00

CPC分类号： H01L27/11526 ,  H01L27/115 ,  H01L27/11546 ,  Y10S148/117 ,  Y10S438/981

摘要： Improved packing density as well as improved performance and manufacturing yield is achieved in an electrically programmable memory by confining floating gate structures between isolation structures covered with a thin nitride layer. The confinement of the floating gate is achieved by planarization, preferably with a self-limiting chemical/mechanical polishing process, to the surface of the nitride layer covering the isolation structures. Gate oxide and control electrode connections can then be formed on a substantially planar surface without compromising the quality of the gate oxide or breakdown voltage the device must withstand for programming. Since severe topology is avoided over which these connections are formed, improved formation of low resistance connections, possibly including metal connections, are possible and allow scaling of transistors of the memory cells to be scaled to sizes not previously possible.

摘要翻译： 通过将浮置栅极结构限制在被薄氮化物层覆盖的隔离结构之间，可在电可编程存储器中实现提高的封装密度以及改进的性能和制造产量。 浮栅的限制是通过平面化，优选采用自限制化学/机械抛光工艺，覆盖覆盖隔离结构的氮化物层的表面来实现的。 然后可以在基本平坦的表面上形成栅极氧化物和控制电极连接，而不会损害器件必须承受编程的栅极氧化物的质量或击穿电压。 由于避免了形成这些连接的严格的拓扑结构，所以可能包括可能包括金属连接的低电阻连接的形成得到改进，并且允许将存储器单元的晶体管缩放到先前不可能的尺寸。

公开(公告)号：US5753525A

公开(公告)日：1998-05-19

申请号：US579025

申请日：1995-12-19

申请人： Louis Lu-Chen Hsu ,  Seiki Ogura ,  James Peng

发明人： Louis Lu-Chen Hsu ,  Seiki Ogura ,  James Peng

IPC分类号： H01L21/8247 ,  H01L27/115

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A method of forming EEPROM cells. The method includes forming a tunnel oxide layer on a wafer and forming floating gates on the tunnel oxide layer with the floating gate having sidewalls. Isolation regions may be formed adjacent the sidewalls. A conformal ONO layer of dielectric is formed on the floating gate and sidewalls, using Chemical Vapor Deposition. Next, a selective etch material layer is deposited on the wafer over the conformal dielectric layer. A polish stop layer is deposited on the wafer over the selective etch material layer to define an upper polishing surface above the floating gate. The exposed polish stop layer and underlying selective etch material are removed by depositing an oxide layer on the polish stop layer and then polishing the deposited layer coplanar with the polish stop layer which is an upper polishing surface above the floating gates. Exposed portions of the polish stop layer are removed to expose the selective etch layer above the floating gates and above sidewall regions adjacent the sidewalls. Then, the exposed selective etch layer is removed, exposing the conformal dielectric layer. Finally, a control gate may be formed by depositing a control gate layer above the floating gate and within the sidewall region and patterning the control gate layer. The patterned control gates extend over the floating gate and along the floating gate sidewalls. The control gate-floating gate capacitor area includes the floating gate sidewalls.

摘要翻译： 一种形成EEPROM单元的方法。 该方法包括在晶片上形成隧道氧化物层，并且在具有侧壁的浮动栅极上形成隧道氧化物层上的浮动栅极。 可以在侧壁附近形成隔离区域。 使用化学气相沉积在浮动栅极和侧壁上形成保形的ONO电介质层。 接下来，在保形电介质层上的晶片上沉积选择性蚀刻材料层。 抛光停止层沉积在选择性蚀刻材料层上的晶片上以限定浮动栅极上方的上抛光表面。 暴露的抛光停止层和下面的选择性蚀刻材料通过在抛光停止层上沉积氧化物层然后用作为在浮动栅极上方的上抛光表面的抛光停止层共面抛光沉积层来去除。 去除抛光停止层的暴露部分以暴露浮动栅极上方的选择性蚀刻层和邻近侧壁的侧壁区域上方。 然后，暴露的选择性蚀刻层被去除，暴露保形介电层。 最后，可以通过在浮动栅极上方和侧壁区域内沉积控制栅极层并且对控制栅极层进行构图来形成控制栅极。 图案化的控制栅极在浮置栅极上延伸并且沿着浮置栅极侧壁延伸。 控制栅极 - 浮动栅极电容器区域包括浮动栅极侧壁。

公开(公告)号：US5389559A

公开(公告)日：1995-02-14

申请号：US161763

申请日：1993-12-02

申请人： Chang-Ming Hsieh ,  Louis L. Hsu ,  Toshio Mii ,  Seiki Ogura ,  Joseph F. Shepard

发明人： Chang-Ming Hsieh ,  Louis L. Hsu ,  Toshio Mii ,  Seiki Ogura ,  Joseph F. Shepard

IPC分类号： H01L21/8242 ,  H01L27/108 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L27/10861 ,  H01L27/10829

摘要： A trench capacitor DRAM cell with Shallow Trench Isolation (STI), a self-aligned buried strap and the method of making the cell. A trench capacitor is defined in a substrate. The trench capacitor's polysilicon (poly) plate is recessed below the surface of the substrate and the trench sidewalls are exposed above the poly. A doped poly layer is deposited over the surface contacting both the sidewall and the trench capacitor's poly plate. Horizontal portions of the poly layer are removed either through chemmech polishing or Reactive Ion Etching (RIE). A shallow trench is formed, removing one formerly exposed trench sidewall and a portion of the trench capacitor's poly plate in order to isolate the DRAM cell from adjacent cells. The remaining poly strap, along the trench sidewall contacting the poly plate, is self aligned to contact the source of the DRAM Pass gate Field Effect Transistor (FET). After the shallow trench is filled with oxide, FET's are formed on the substrate, completing the cell. In an alternate embodiment, instead of recessing the poly plate, a shallow trench is formed spanning the entire width of the trench capacitor. The deposited polysilicon is selectively removed, having straps that strap the poly plate to the shallow trench sidewall.

摘要翻译： 具有浅沟槽隔离（STI）的沟槽电容器DRAM单元，自对准掩埋带和制造电池的方法。 沟槽电容器限定在衬底中。 沟槽电容器的多晶硅（poly）板在衬底的表面下方凹入，并且沟槽侧壁暴露在聚合物上方。 在与侧壁和沟槽电容器的多晶硅板接触的表面上沉积掺杂的多晶硅层。 通过化学抛光或反应离子蚀刻（RIE）去除多层的水平部分。 形成浅沟槽，去除一个以前暴露的沟槽侧壁和沟槽电容器的多晶片的一部分，以便将DRAM单元与相邻单元隔离。 沿着与多晶硅板接触的沟槽侧壁的剩余多晶带自对准以接触DRAM通过栅极场效应晶体管（FET）的源极。 在浅沟槽充满氧化物之后，在衬底上形成FET，从而完成电池。 在替代实施例中，代替凹陷多晶硅，形成跨越沟槽电容器的整个宽度的浅沟槽。 选择性地去除沉积的多晶硅，具有将多晶板绑定到浅沟槽侧壁的带。

公开(公告)号：US5528062A

公开(公告)日：1996-06-18

申请号：US900041

申请日：1992-06-17

申请人： Chang-Ming Hsieh ,  Louis L. C. Hsu ,  Seiki Ogura

发明人： Chang-Ming Hsieh ,  Louis L. C. Hsu ,  Seiki Ogura

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L27/10829 ,  H01L27/10823

摘要： A high density, DRAM cell array with a very short channel, vertical gate transfer transistor that can be manufactured using conventional photolithography process steps. The conventional four-by-four DRAM array shown schematically in FIG. 1a is rearranged to the shared-gate, double-bit array shown schematically in FIG. 1b. Trench storage capacitors and vertical FET transistors are arranged in pairs with a common vertical gate and a common substrate, allowing both bit and substrate contacts to be shared by adjacent cells.

摘要翻译： 具有非常短的通道的高密度DRAM单元阵列，垂直栅极转移晶体管可以使用常规光刻工艺步骤制造。 图1中示意性示出的常规四乘四DRAM阵列。 1a被重新布置到图1中示意性示出的共享门双位阵列。 1b。 沟槽存储电容器和垂直FET晶体管与公共垂直栅极和公共衬底成对配置，允许位和衬底触点由相邻单元共享。

公开(公告)号：US5340759A

公开(公告)日：1994-08-23

申请号：US113941

申请日：1993-08-30

申请人： Chang-Ming Hsieh ,  Louis L. C. Hsu ,  Seiki Ogura

发明人： Chang-Ming Hsieh ,  Louis L. C. Hsu ,  Seiki Ogura

IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L27/12 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L29/78642 ,  H01L27/1203

摘要： A field effect transistor (FET) with a vertical gate and a very thin channel sandwiched between source and drain layers. In a preferred embodiment of the invention, the FET is formed on a silicon on insulator (SOI) substrate with the silicon layer serving as the first layer (e.g., the source layer). A low temperature epitaxial (LTE) process is used to form a very thin (e.g., 0.1 .mu.m) channel, and a chemically vapor deposited polysilicon layer forms the top layer (e.g., the drain layer). An opening is etched through the three layers to the insulator substrate and its wall is oxidized, forming a gate oxide. Polysilicon is deposited to fill the opening and form the vertical gate.

摘要翻译： 具有垂直栅极和夹在源极和漏极层之间的非常薄的沟道的场效应晶体管（FET）。 在本发明的一个优选实施例中，FET在硅绝缘体（SOI）衬底上形成，硅层用作第一层（例如，源层）。 使用低温外延（LTE）工艺来形成非常薄（例如0.1μm）的通道，并且化学气相沉积的多晶硅层形成顶层（例如，漏层）。 通过三层蚀刻开口到绝缘体衬底，并且其壁被氧化，形成栅极氧化物。 沉积多晶硅以填充开口并形成垂直浇口。