公开(公告)号：US07202719B2

公开(公告)日：2007-04-10

申请号：US10955469

申请日：2004-09-30

申请人： Manuel P. Gabato, Jr. ,  Joseph A. Charaska ,  Paul H. Gailus

发明人： Manuel P. Gabato, Jr. ,  Joseph A. Charaska ,  Paul H. Gailus

IPC分类号： H03L7/06

CPC分类号： H03L7/0812 ,  H03K5/1504 ,  H03K2005/00032 ,  H03L7/07 ,  H03L7/16

摘要： A DPC (200) that includes: a frequency source (20); a delay-locked loop (220) for receiving a clock signal and generating a plurality of phase-shifted clock signals; a control device (280) having a DPS (282) and a DAC (284) for receiving an input signal identifying a desired frequency for a synthesized signal; a selection circuit (270) for receiving the plurality of phase-shifted clock signals, selecting a sequence of the phase-shifted clock signals and outputting a coarse synthesized signal; a variable delay cell (290) having a first input coupled to the selection circuit to receive the coarse synthesized signal and a second input coupled to the control device for receiving a fine tune adjustment signal to modify the coarse synthesized signal to generate the synthesized signal (292) having substantially the desired frequency. The DPC further includes training apparatus for calibrating the DPC.

摘要翻译： DPC（200），其包括：频率源（20）; 延迟锁定环路（220），用于接收时钟信号并产生多个相移时钟信号; 具有DPS（282）和DAC（284）的控制装置（280），用于接收标识合成信号的期望频率的输入信号; 选择电路（270），用于接收多个相移时钟信号，选择相移时钟信号的序列并输出粗略的合成信号; 可变延迟单元（290），其具有耦合到所述选择电路以接收所述粗略合成信号的第一输入和耦合到所述控制装置的第二输入，用于接收微调调整信号以修改所述粗合成信号以产生所述合成信号（ 292）具有基本上所需的频率。 DPC还包括用于校准DPC的训练装置。

公开(公告)号：US07109766B2

公开(公告)日：2006-09-19

申请号：US10830337

申请日：2004-04-22

申请人： Jeffrey B. White ,  Joseph A. Charaska ,  Manuel P. Gabato, Jr. ,  Paul H. Gailus ,  Robert E. Stengel

发明人： Jeffrey B. White ,  Joseph A. Charaska ,  Manuel P. Gabato, Jr. ,  Paul H. Gailus ,  Robert E. Stengel

IPC分类号： H03L7/08

CPC分类号： H03L7/16 ,  H03K5/133 ,  H03K2005/00026 ,  H03K2005/00058 ,  H03L7/0812

摘要： A delay-locked loop 300 that includes: an adjustable frequency source (320) for generating a clock signal (322) having an adjustable frequency; an adjustment and tap selection controller (310) for determining a first frequency as a function of a second frequency and for causing the frequency source to adjust the frequency of the clock signal to substantially the first frequency, the second frequency being the desired frequency of a first output signal; a delay line (330) configured to receive the clock signal for generating a plurality of phase-shifted clock signals; and a first selection circuit (370) for receiving the plurality of phase-shifted clock signals and for selecting, one at a time and under the control of the adjustment and tap selection controller, a first sequence of the phase-shifted clock signals for generating the first output signal having substantially the second frequency.

摘要翻译： 延迟锁定环路300，其包括：用于产生具有可调频率的时钟信号（322）的可调频率源（320） 调整和抽头选择控制器（310），用于根据第二频率确定第一频率，并使频率源将时钟信号的频率调整到基本上第一频率;第二频率是期望的频率 第一输出信号; 延迟线（330），被配置为接收用于产生多个相移时钟信号的时钟信号; 以及第一选择电路（370），用于接收多个相移时钟信号，并用于在调整和分接选择控制器的控制下一次一个地选择第一个相移时钟信号序列，用于产生 第一输出信号具有基本上第二频率。

公开(公告)号：US20090081984A1

公开(公告)日：2009-03-26

申请号：US11860636

申请日：2007-09-25

申请人： PAUL H. GAILUS ,  JOHN J. BOZEKI ,  JOSEPH A. CHARASKA ,  VADIM DUBOV ,  MANUEL P. GABATO, JR. ,  ARMANDO J. GONZALEZ

发明人： PAUL H. GAILUS ,  JOHN J. BOZEKI ,  JOSEPH A. CHARASKA ,  VADIM DUBOV ,  MANUEL P. GABATO, JR. ,  ARMANDO J. GONZALEZ

IPC分类号： H04B1/26 ,  H03B21/00 ,  H03L1/00

CPC分类号： H03L7/1974

摘要： A frequency synthesizer includes: a frequency source generating a reference signal that includes a plurality of pulses having periodicity based on a reference frequency; a feedback loop that includes, a phase detector circuit, a loop filter, a controlled oscillator that generates an output signal at an output, and a loop divide circuit; a non-linear circuit element at an input of the phase detector circuit, which generates intermodulation distortion that causes at least one spurious signal at the output; and a controller controlling the loop divide circuit and the non-linear circuit element. The frequency synthesizer further includes a dither circuit that adjusts the timing of some of the pulses of the reference signal based on a parameter provided by the controller to the non-linear circuit element, thereby, providing a jittered reference signal to the non-linear circuit element for attenuating the at least one spurious signal at the output.

摘要翻译： 频率合成器包括：频率源，产生包括基于参考频率具有周期性的多个脉冲的参考信号; 反馈回路，包括相位检测器电路，环路滤波器，在输出端产生输出信号的受控振荡器和环路除法电路; 在相位检测器电路的输入处的非线性电路元件，其产生在输出端引起至少一个杂散信号的互调失真; 以及控制环路分割电路和非线性电路元件的控制器。 频率合成器还包括抖动电路，其基于由控制器向非线性电路元件提供的参数来调整参考信号的一些脉冲的定时，从而向非线性电路提供抖动参考信号 元件，用于衰减输出端的至少一个杂散信号。

公开(公告)号：US07929929B2

公开(公告)日：2011-04-19

申请号：US11860636

申请日：2007-09-25

申请人： Paul H. Gailus ,  John J. Bozeki ,  Joseph A. Charaska ,  Vadim Dubov ,  Manuel P. Gabato, Jr. ,  Armando J Gonzalez

发明人： Paul H. Gailus ,  John J. Bozeki ,  Joseph A. Charaska ,  Vadim Dubov ,  Manuel P. Gabato, Jr. ,  Armando J Gonzalez

IPC分类号： H04B1/18

CPC分类号： H03L7/1974

摘要： A frequency synthesizer includes: a frequency source generating a reference signal that includes a plurality of pulses having periodicity based on a reference frequency; a feedback loop that includes, a phase detector circuit, a loop filter, a controlled oscillator that generates an output signal at an output, and a loop divide circuit; a non-linear circuit element at an input of the phase detector circuit, which generates intermodulation distortion that causes at least one spurious signal at the output; and a controller controlling the loop divide circuit and the non-linear circuit element. The frequency synthesizer further includes a dither circuit that adjusts the timing of some of the pulses of the reference signal based on a parameter provided by the controller to the non-linear circuit element, thereby, providing a jittered reference signal to the non-linear circuit element for attenuating the at least one spurious signal at the output.

摘要翻译： 频率合成器包括：频率源，产生包括基于参考频率具有周期性的多个脉冲的参考信号; 反馈回路，包括相位检测器电路，环路滤波器，在输出端产生输出信号的受控振荡器和环路除法电路; 在相位检测器电路的输入处的非线性电路元件，其产生在输出端引起至少一个杂散信号的互调失真; 以及控制环路分割电路和非线性电路元件的控制器。 频率合成器还包括抖动电路，其基于由控制器向非线性电路元件提供的参数来调整参考信号的一些脉冲的定时，从而向非线性电路提供抖动参考信号 元件，用于衰减输出端的至少一个杂散信号。

公开(公告)号：US07786772B2

公开(公告)日：2010-08-31

申请号：US12131035

申请日：2008-05-30

申请人： Manuel P. Gabato, Jr. ,  John J. Bozeki ,  Joseph A. Charaska ,  Paul H. Gailus

发明人： Manuel P. Gabato, Jr. ,  John J. Bozeki ,  Joseph A. Charaska ,  Paul H. Gailus

IPC分类号： H03L7/06

CPC分类号： H03L7/1974 ,  H03L7/0893

摘要： A method and apparatus for reducing in-band spurs in a fractional-N synthesizer (100) includes generating a compensated current signal by a charge pump (108) coupled to a phase detector (106). The compensated current signal includes in-band spurs having frequencies within a frequency bandwidth associated with a loop filter (110). The method then includes selectively dithering the compensated current signal with a sufficient dither level to spread the frequencies of in-band spurs beyond the frequency bandwidth associated with the loop filter (110). The dithered compensated current signal is then passed through the loop filter (110) for filtering the in-band spurs having frequencies beyond the frequency bandwidth. The method then includes generating a voltage controlled oscillator (VCO) signal with reduced in-band spurs proportional to the filtered compensated current signal.

摘要翻译： 用于减小分数N合成器（100）中的带内杂散的方法和装置包括通过耦合到相位检测器（106）的电荷泵（108）产生补偿的电流信号。 经补偿的电流信号包括具有与环路滤波器（110）相关联的频率带宽内的频率的带内杂散。 该方法然后包括以足够的抖动电平选择性地使经补偿的电流信号抖动，以将带内杂散的频率扩展到与环路滤波器（110）相关联的频率带宽之外。 抖动补偿电流信号然后通过环路滤波器（110），用于对频率超过频率带宽的带内杂散进行滤波。 该方法然后包括产生与经滤波的补偿电流信号成比例的减小的带内杂散的压控振荡器（VCO）信号。

公开(公告)号：US20090295435A1

公开(公告)日：2009-12-03

申请号：US12131035

申请日：2008-05-30

申请人： Manuel P. Gabato, JR. ,  John J. Bozeki ,  Joseph A. Charaska ,  Paul H. Gailus

发明人： Manuel P. Gabato, JR. ,  John J. Bozeki ,  Joseph A. Charaska ,  Paul H. Gailus

IPC分类号： H03B21/00

CPC分类号： H03L7/1974 ,  H03L7/0893

摘要： A method and apparatus for reducing in-band spurs in a fractional-N synthesizer (100) includes generating a compensated current signal by a charge pump (108) coupled to a phase detector (106). The compensated current signal includes in-band spurs having frequencies within a frequency bandwidth associated with a loop filter (110). The method then includes selectively dithering the compensated current signal with a sufficient dither level to spread the frequencies of in-band spurs beyond the frequency bandwidth associated with the loop filter (110). The dithered compensated current signal is then passed through the loop filter (110) for filtering the in-band spurs having frequencies beyond the frequency bandwidth. The method then includes generating a voltage controlled oscillator (VCO) signal with reduced in-band spurs proportional to the filtered compensated current signal.

摘要翻译： 用于减小分数N合成器（100）中的带内杂散的方法和装置包括通过耦合到相位检测器（106）的电荷泵（108）产生补偿的电流信号。 经补偿的电流信号包括具有与环路滤波器（110）相关联的频率带宽内的频率的带内杂散。 该方法然后包括以足够的抖动电平选择性地使经补偿的电流信号抖动，以将带内杂散的频率扩展到与环路滤波器（110）相关联的频率带宽之外。 抖动补偿电流信号然后通过环路滤波器（110），用于对频率超过频率带宽的带内杂散进行滤波。 该方法然后包括产生与经滤波的补偿电流信号成比例的减小的带内杂散的压控振荡器（VCO）信号。