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公开(公告)号：US07929929B2
公开(公告)日：2011-04-19
申请号：US11860636
申请日：2007-09-25
申请人： Paul H. Gailus , John J. Bozeki , Joseph A. Charaska , Vadim Dubov , Manuel P. Gabato, Jr. , Armando J Gonzalez
发明人： Paul H. Gailus , John J. Bozeki , Joseph A. Charaska , Vadim Dubov , Manuel P. Gabato, Jr. , Armando J Gonzalez
IPC分类号： H04B1/18
CPC分类号： H03L7/1974
摘要： A frequency synthesizer includes: a frequency source generating a reference signal that includes a plurality of pulses having periodicity based on a reference frequency; a feedback loop that includes, a phase detector circuit, a loop filter, a controlled oscillator that generates an output signal at an output, and a loop divide circuit; a non-linear circuit element at an input of the phase detector circuit, which generates intermodulation distortion that causes at least one spurious signal at the output; and a controller controlling the loop divide circuit and the non-linear circuit element. The frequency synthesizer further includes a dither circuit that adjusts the timing of some of the pulses of the reference signal based on a parameter provided by the controller to the non-linear circuit element, thereby, providing a jittered reference signal to the non-linear circuit element for attenuating the at least one spurious signal at the output.
摘要翻译： 频率合成器包括：频率源，产生包括基于参考频率具有周期性的多个脉冲的参考信号; 反馈回路，包括相位检测器电路，环路滤波器，在输出端产生输出信号的受控振荡器和环路除法电路; 在相位检测器电路的输入处的非线性电路元件，其产生在输出端引起至少一个杂散信号的互调失真; 以及控制环路分割电路和非线性电路元件的控制器。 频率合成器还包括抖动电路，其基于由控制器向非线性电路元件提供的参数来调整参考信号的一些脉冲的定时，从而向非线性电路提供抖动参考信号 元件，用于衰减输出端的至少一个杂散信号。
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2.发明授权公开(公告)号：US07786772B2
公开(公告)日：2010-08-31
申请号：US12131035
申请日：2008-05-30
IPC分类号： H03L7/06
CPC分类号： H03L7/1974 , H03L7/0893
摘要： A method and apparatus for reducing in-band spurs in a fractional-N synthesizer (100) includes generating a compensated current signal by a charge pump (108) coupled to a phase detector (106). The compensated current signal includes in-band spurs having frequencies within a frequency bandwidth associated with a loop filter (110). The method then includes selectively dithering the compensated current signal with a sufficient dither level to spread the frequencies of in-band spurs beyond the frequency bandwidth associated with the loop filter (110). The dithered compensated current signal is then passed through the loop filter (110) for filtering the in-band spurs having frequencies beyond the frequency bandwidth. The method then includes generating a voltage controlled oscillator (VCO) signal with reduced in-band spurs proportional to the filtered compensated current signal.
摘要翻译： 用于减小分数N合成器（100）中的带内杂散的方法和装置包括通过耦合到相位检测器（106）的电荷泵（108）产生补偿的电流信号。 经补偿的电流信号包括具有与环路滤波器（110）相关联的频率带宽内的频率的带内杂散。 该方法然后包括以足够的抖动电平选择性地使经补偿的电流信号抖动，以将带内杂散的频率扩展到与环路滤波器（110）相关联的频率带宽之外。 抖动补偿电流信号然后通过环路滤波器（110），用于对频率超过频率带宽的带内杂散进行滤波。 该方法然后包括产生与经滤波的补偿电流信号成比例的减小的带内杂散的压控振荡器（VCO）信号。
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3.发明申请公开(公告)号：US20090295435A1
公开(公告)日：2009-12-03
申请号：US12131035
申请日：2008-05-30
IPC分类号： H03B21/00
CPC分类号： H03L7/1974 , H03L7/0893
摘要： A method and apparatus for reducing in-band spurs in a fractional-N synthesizer (100) includes generating a compensated current signal by a charge pump (108) coupled to a phase detector (106). The compensated current signal includes in-band spurs having frequencies within a frequency bandwidth associated with a loop filter (110). The method then includes selectively dithering the compensated current signal with a sufficient dither level to spread the frequencies of in-band spurs beyond the frequency bandwidth associated with the loop filter (110). The dithered compensated current signal is then passed through the loop filter (110) for filtering the in-band spurs having frequencies beyond the frequency bandwidth. The method then includes generating a voltage controlled oscillator (VCO) signal with reduced in-band spurs proportional to the filtered compensated current signal.
摘要翻译： 用于减小分数N合成器（100）中的带内杂散的方法和装置包括通过耦合到相位检测器（106）的电荷泵（108）产生补偿的电流信号。 经补偿的电流信号包括具有与环路滤波器（110）相关联的频率带宽内的频率的带内杂散。 该方法然后包括以足够的抖动电平选择性地使经补偿的电流信号抖动，以将带内杂散的频率扩展到与环路滤波器（110）相关联的频率带宽之外。 抖动补偿电流信号然后通过环路滤波器（110），用于对频率超过频率带宽的带内杂散进行滤波。 该方法然后包括产生与经滤波的补偿电流信号成比例的减小的带内杂散的压控振荡器（VCO）信号。
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公开(公告)号：US07109766B2
公开(公告)日：2006-09-19
申请号：US10830337
申请日：2004-04-22
申请人： Jeffrey B. White , Joseph A. Charaska , Manuel P. Gabato, Jr. , Paul H. Gailus , Robert E. Stengel
发明人： Jeffrey B. White , Joseph A. Charaska , Manuel P. Gabato, Jr. , Paul H. Gailus , Robert E. Stengel
IPC分类号： H03L7/08
CPC分类号： H03L7/16 , H03K5/133 , H03K2005/00026 , H03K2005/00058 , H03L7/0812
摘要： A delay-locked loop 300 that includes: an adjustable frequency source (320) for generating a clock signal (322) having an adjustable frequency; an adjustment and tap selection controller (310) for determining a first frequency as a function of a second frequency and for causing the frequency source to adjust the frequency of the clock signal to substantially the first frequency, the second frequency being the desired frequency of a first output signal; a delay line (330) configured to receive the clock signal for generating a plurality of phase-shifted clock signals; and a first selection circuit (370) for receiving the plurality of phase-shifted clock signals and for selecting, one at a time and under the control of the adjustment and tap selection controller, a first sequence of the phase-shifted clock signals for generating the first output signal having substantially the second frequency.
摘要翻译： 延迟锁定环路300，其包括：用于产生具有可调频率的时钟信号（322）的可调频率源（320） 调整和抽头选择控制器（310），用于根据第二频率确定第一频率，并使频率源将时钟信号的频率调整到基本上第一频率;第二频率是期望的频率 第一输出信号; 延迟线（330），被配置为接收用于产生多个相移时钟信号的时钟信号; 以及第一选择电路（370），用于接收多个相移时钟信号，并用于在调整和分接选择控制器的控制下一次一个地选择第一个相移时钟信号序列，用于产生 第一输出信号具有基本上第二频率。
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公开(公告)号：US07202719B2
公开(公告)日：2007-04-10
申请号：US10955469
申请日：2004-09-30
IPC分类号： H03L7/06
CPC分类号： H03L7/0812 , H03K5/1504 , H03K2005/00032 , H03L7/07 , H03L7/16
摘要： A DPC (200) that includes: a frequency source (20); a delay-locked loop (220) for receiving a clock signal and generating a plurality of phase-shifted clock signals; a control device (280) having a DPS (282) and a DAC (284) for receiving an input signal identifying a desired frequency for a synthesized signal; a selection circuit (270) for receiving the plurality of phase-shifted clock signals, selecting a sequence of the phase-shifted clock signals and outputting a coarse synthesized signal; a variable delay cell (290) having a first input coupled to the selection circuit to receive the coarse synthesized signal and a second input coupled to the control device for receiving a fine tune adjustment signal to modify the coarse synthesized signal to generate the synthesized signal (292) having substantially the desired frequency. The DPC further includes training apparatus for calibrating the DPC.
摘要翻译： DPC（200），其包括：频率源（20）; 延迟锁定环路（220），用于接收时钟信号并产生多个相移时钟信号; 具有DPS（282）和DAC（284）的控制装置（280），用于接收标识合成信号的期望频率的输入信号; 选择电路（270），用于接收多个相移时钟信号，选择相移时钟信号的序列并输出粗略的合成信号; 可变延迟单元（290），其具有耦合到所述选择电路以接收所述粗略合成信号的第一输入和耦合到所述控制装置的第二输入，用于接收微调调整信号以修改所述粗合成信号以产生所述合成信号（ 292）具有基本上所需的频率。 DPC还包括用于校准DPC的训练装置。
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6.发明申请SYSTEM AND METHOD FOR REDUCING TRANSIENT RESPONSES IN A PHASE LOCK LOOP WITH VARIABLE OSCILLATOR GAIN 有权在具有可变振荡器增益的相位锁定环中减少瞬态响应的系统和方法公开(公告)号：US20080129388A1
公开(公告)日：2008-06-05
申请号：US11564965
申请日：2006-11-30
CPC分类号： H03L7/0893 , H03L7/107 , H03L7/1072 , H03L7/18
摘要： A system and method for reducing the transient responses in a phase lock loop (PLL) (100) with variable oscillator gain is disclosed. The system includes a charge pump (104) having an adapt mode and a normal mode of operation. The charge pump (104) also includes controlled trickle currents from current sources (208), (210) which are applied to the output (105), (107) of charge pump (104) to minimize the transient responses of the PLL (100). A programmable delay is provided in the charge pump (104) and is configured using a controller (122) based on the variable oscillator gain for the PLL (100). The configured programmable delay is used in the adapt mode of operation for adding a trickle current from the current source (210) to the adapt mode output (107).
摘要翻译： 公开了一种用于减少具有可变振荡器增益的锁相环（PLL）（100）中的瞬态响应的系统和方法。 该系统包括具有适应模式和正常操作模式的电荷泵（104）。 电荷泵（104）还包括来自电流源（208），（210）的控制的涓流电流，其被施加到电荷泵（104）的输出（105），（107），以最小化PLL（100）的瞬态响应 ）。 在电荷泵（104）中提供可编程延迟，并且使用基于PLL（100）的可变振荡器增益的控制器（122）来配置可编程延迟。 配置的可编程延迟用于适应操作模式，用于将来自当前源（210）的涓流电流添加到适配模式输出（107）。
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7.发明授权System and method for reducing transient responses in a phase lock loop with variable oscillator gain 有权用于减少具有可变振荡器增益的锁相环中瞬态响应的系统和方法公开(公告)号：US07504893B2
公开(公告)日：2009-03-17
申请号：US11564965
申请日：2006-11-30
IPC分类号： H03L7/089
CPC分类号： H03L7/0893 , H03L7/107 , H03L7/1072 , H03L7/18
摘要： A system and method for reducing the transient responses in a phase lock loop (PLL) (100) with variable oscillator gain is disclosed. The system includes a charge pump (104) having an adapt mode and a normal mode of operation. The charge pump (104) also includes controlled trickle currents from current sources (208), (210) which are applied to the output (105), (107) of charge pump (104) to minimize the transient responses of the PLL (100). A programmable delay is provided in the charge pump (104) and is configured using a controller (122) based on the variable oscillator gain for the PLL (100). The configured programmable delay is used in the adapt mode of operation for adding a trickle current from the current source (210) to the adapt mode output (107).
摘要翻译： 公开了一种用于减少具有可变振荡器增益的锁相环（PLL）（100）中的瞬态响应的系统和方法。 该系统包括具有适应模式和正常操作模式的电荷泵（104）。 电荷泵（104）还包括来自电流源（208），（210）的控制的涓流电流，其被施加到电荷泵（104）的输出（105），（107），以最小化PLL（100）的瞬态响应 ）。 在电荷泵（104）中提供可编程延迟，并且使用基于PLL（100）的可变振荡器增益的控制器（122）来配置可编程延迟。 配置的可编程延迟用于适应操作模式，用于将来自当前源（210）的涓流电流添加到适配模式输出（107）。
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8.发明授权System and method for reducing transient response in a fractional N phase lock loop 有权用于减小分数N个锁相环中的瞬态响应的系统和方法公开(公告)号：US07170322B2
公开(公告)日：2007-01-30
申请号：US11139160
申请日：2005-05-28
IPC分类号： H03L7/06
CPC分类号： H03L7/0898 , H03L7/107 , H03L7/1072 , H03L7/1976
摘要： A system and method for reducing a transient response in a phase lock loop (PLL) (100) is disclosed. The system includes an adapt mode charge pump (204), a normal mode charge pump (206) and the use of controlled trickle currents (208), (210) applied to those charge pumps to minimize a transient response of the PLL (100).
摘要翻译： 公开了一种用于减小锁相环（PLL）（100）中的瞬态响应的系统和方法。 该系统包括适应模式电荷泵（204），正常模式电荷泵（206）以及施加到这些电荷泵的受控涓流（208），（210）的使用以最小化PLL（100）的瞬态响应， 。
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9.发明授权Method and apparatus to facilitate the provision and use of a plurality of varactors with a plurality of switches 有权有助于提供和使用具有多个开关的多个变容二极管的方法和装置公开(公告)号：US07646257B2
公开(公告)日：2010-01-12
申请号：US11621769
申请日：2007-01-10
申请人： Paul H. Gailus , Joseph A. Charaska
发明人： Paul H. Gailus , Joseph A. Charaska
IPC分类号： H03B5/12
CPC分类号： H03J3/20 , H03B2201/0208 , H03J2200/10
摘要： A plurality of varactors are coupled via a first electrode to a shared terminal that in turn can operably couple to a source of control voltage. A second electrode for each varactor couples to a corresponding switch, where each switch couples to at least two different voltage levels. So configured, the second electrode of each varactor can be individually connected to either of two voltage levels. This can be leveraged to control, in coarse steps, the overall aggregate effective capacitance presented by these components. At least some of these varactors can have differing corresponding capacitances, the specific values of which can be selected in order to facilitate relatively equal spacing and substantially equal rates of reactance change versus the control voltage value between aggregate-capacitive reactance ranges as correspond to differing settings for the switches at various levels for the control voltage source.
摘要翻译： 多个变容二极管经由第一电极耦合到共享端子，共享端子又可操作地耦合到控制电压源。 每个变容二极管的第二电极耦合到相应的开关，其中每个开关耦合到至少两个不同的电压电平。 如此配置，每个变容二极管的第二电极可以单独连接到两个电压电平中的任一个。 这可以用来粗略地控制由这些组件提供的总体有效电容。 这些变容二极管中的至少一些可以具有不同的对应电容，其特定值可以被选择以便于相对于不同的设置来促进相对等间隔和基本相等的电抗变化率与聚集电容电抗范围之间的控制电压值 用于控制电压源的各种开关。
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10.发明授权
公开(公告)号：US5379039A
公开(公告)日：1995-01-03
申请号：US96386
申请日：1993-07-26
IPC分类号： H03M3/02
摘要： An analog-to-digital (A/D) circuit comprising a multi-pole gain stage, a quantizer, and a feedback stage is stabilized when an analog input signal is excessive in the following manner. A stabilization detector continually samples a representation of stabilization of the A/D circuit. When the representation of stabilization is unfavorable, the stabilization detector increases, via a stabilizer, phase margin by adjusting the pole locations of the multi-pole gain stage based on the degree of unfavorability of the representation of stabilization. With the increased phase margin, the A/D circuit continues to provide digital representations of the analog input signal.
摘要翻译： 当模拟输入信号以下列方式过大时，包括多极增益级，量化器和反馈级的模数（A / D）电路是稳定的。 稳定检测器连续地采样A / D电路的稳定化表示。 当稳定化的表现不利时，稳定检测器通过稳定器增加相位裕度，通过基于稳定化表示的不利程度来调节多极增益级的极点位置。 随着相位裕量的增加，A / D电路继续提供模拟输入信号的数字表示。
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