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公开(公告)号：US09135067B2
公开(公告)日：2015-09-15
申请号：US13780197
申请日：2013-02-28
发明人： Debasish Chandra
CPC分类号： G06F9/5016 , G06F9/30043 , G06F9/3824 , G06F9/3836 , G06F9/4812 , G06F9/4881 , G06F9/50 , G06F9/5011 , G06F2209/507
摘要： Methods and systems that reduce the number of instance of a shared resource needed for a processor to perform an operation and/or execute a process without impacting function are provided. a method of processing in a processor is provided. Aspects include determining that an operation to be performed by the processor will require the use of a shared resource. A command can be issued to cause a second operation to not use the shared resources N cycles later. The shared resource can then be used for a first aspect of the operation at cycle X and then used for a second aspect of the operation at cycle X+N. The second operation may be rescheduled according to embodiments.
摘要翻译： 提供了减少处理器执行操作所需的共享资源的实例数量和/或执行不影响功能的过程的方法和系统。 提供了一种处理器中的处理方法。 方面包括确定要由处理器执行的操作将需要使用共享资源。 可以发出一个命令，导致第二个操作在N个周期后不使用共享资源。 共享资源然后可以用于周期X上的操作的第一方面，然后用于周期X + N处的操作的第二方面。 可以根据实施例重新安排第二操作。
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公开(公告)号：US20140281413A1
公开(公告)日：2014-09-18
申请号：US13828747
申请日：2013-03-14
发明人： Qian WANG , Ranganathan Sudhakar
IPC分类号： G06F9/30
CPC分类号： G06F9/30098 , G06F9/30032 , G06F9/3826 , G06F9/3838 , G06F9/384
摘要： Methods and systems that allow the processor to effectively and efficiently reduce or eliminate the latency associated with instructions that copy the value of one register to another register. A processor includes a superforwarding table, a superforwarding logic block, and a computation engine. The superforwarding table stores an entry, wherein the entry has a valid bit, a key field, and a forward field. The superforwarding logic block determines which register contains the information needed for an instruction. The computation engine executes instructions.
摘要翻译： 允许处理器有效地降低或消除与将一个寄存器的值复制到另一个寄存器的指令相关联的延迟的方法和系统。 处理器包括超级表，超前逻辑块和计算引擎。 超级表格存储条目，其中条目具有有效位，键字段和转发字段。 超前逻辑块确定哪个寄存器包含指令所需的信息。 计算引擎执行指令。
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公开(公告)号：US20140258667A1
公开(公告)日：2014-09-11
申请号：US13789394
申请日：2013-03-07
发明人： Ranganathan Sudhakar
IPC分类号： G11C7/10
CPC分类号： G11C7/1039 , G06F9/30043
摘要： A processor is configured to evaluate memory operation bonding criteria to selectively identify memory operation bonding opportunities within a memory access plan. Memory operations are combined in response to the memory operation bonding opportunities to form a revised memory access plan with accelerated memory access.
摘要翻译： 处理器被配置为评估存储器操作绑定标准以选择性地识别存储器访问计划中的存储器操作绑定机会。 响应于存储器操作结合机会来组合存储器操作以形成具有加速存储器访问的经修改的存储器存取方案。
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公开(公告)号：US20140244933A1
公开(公告)日：2014-08-28
申请号：US13781319
申请日：2013-02-28
发明人： Ranganathan Sudhakar , Parthiv Pota
IPC分类号： G06F12/08
CPC分类号： G06F12/0864 , G06F3/0625 , G06F9/3802 , G06F12/0215 , G06F12/0855 , G06F2212/1028 , G06F2212/452 , Y02D10/13
摘要： Methods and systems that identify and power up ways for future instructions are provided. A processor includes an n-way set associative cache and an instruction fetch unit. The n-way set associative cache is configured to store instructions. The instruction fetch unit is in communication with the n-way set associative cache and is configured to power up a first way, where a first indication is associated with an instruction and indicates the way where a future instruction is located and where the future instruction is two or more instructions ahead of the current instruction.
摘要翻译： 提供了识别和加强未来指导方法的方法和系统。 处理器包括n路组关联高速缓存和指令提取单元。 n路组关联缓存配置为存储指令。 指令提取单元与n路组关联高速缓存通信，并且被配置为以第一方式加电，其中第一指示与指令相关联并且指示未来指令所在的方式以及未来指令在哪里 当前指令之前的两个或更多个指令。
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公开(公告)号：US09235510B2
公开(公告)日：2016-01-12
申请号：US13683875
申请日：2012-11-21
CPC分类号： G06F12/08 , G06F12/1045 , G06F12/109 , G06F12/14 , G06F12/1491
摘要： A computer includes a memory and a processor connected to the memory. The processor includes memory segment configuration registers to store defined memory address segments and defined memory address segment attributes such that the processor operates in accordance with the defined memory address segments and defined memory address segment attributes to allow kernel mode access to user space virtual addresses for enhanced kernel mode memory capacity.
摘要翻译： 计算机包括存储器和连接到存储器的处理器。 处理器包括存储器段配置寄存器，用于存储定义的存储器地址段和定义的存储器地址段属性，使得处理器根据所定义的存储器地址段和定义的存储器地址段属性进行操作，以允许内核模式访问用户空间虚拟地址以增强 内核模式内存容量。
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公开(公告)号：US20150370605A1
公开(公告)日：2015-12-24
申请号：US14837109
申请日：2015-08-27
发明人： Debasish CHANDRA
CPC分类号： G06F9/5016 , G06F9/30043 , G06F9/3824 , G06F9/3836 , G06F9/4812 , G06F9/4881 , G06F9/50 , G06F9/5011 , G06F2209/507
摘要： Methods and systems that reduce the number of instance of a shared resource needed for a processor to perform an operation and/or execute a process without impacting function are provided. a method of processing in a processor is provided. Aspects include determining that an operation to be performed by the processor will require the use of a shared resource. A command can be issued to cause a second operation to not use the shared resources N cycles later. The shared resource can then be used for a first aspect of the operation at cycle X and then used for a second aspect of the operation at cycle X+N. The second operation may be rescheduled according to embodiments.
摘要翻译： 提供了减少处理器执行操作所需的共享资源的实例数量和/或执行不影响功能的过程的方法和系统。 提供了一种处理器中的处理方法。 方面包括确定要由处理器执行的操作将需要使用共享资源。 可以发出一个命令，导致第二个操作在N个周期后不使用共享资源。 共享资源然后可以用于周期X上的操作的第一方面，然后用于周期X + N处的操作的第二方面。 可以根据实施例重新安排第二操作。
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公开(公告)号：US20140245317A1
公开(公告)日：2014-08-28
申请号：US13780197
申请日：2013-02-28
发明人： Debasish CHANDRA
IPC分类号： G06F9/50
CPC分类号： G06F9/5016 , G06F9/30043 , G06F9/3824 , G06F9/3836 , G06F9/4812 , G06F9/4881 , G06F9/50 , G06F9/5011 , G06F2209/507
摘要： Methods and systems that reduce the number of instance of a shared resource needed for a processor to perform an operation and/or execute a process without impacting function are provided. a method of processing in a processor is provided. Aspects include determining that an operation to be performed by the processor will require the use of a shared resource. A command can be issued to cause a second operation to not use the shared resources N cycles later. The shared resource can then be used for a first aspect of the operation at cycle X and then used for a second aspect of the operation at cycle X+N. The second operation may be rescheduled according to embodiments.
摘要翻译： 提供了减少处理器执行操作所需的共享资源的实例数量和/或执行不影响功能的过程的方法和系统。 提供了一种处理器中的处理方法。 方面包括确定要由处理器执行的操作将需要使用共享资源。 可以发出一个命令，导致第二个操作在N个周期后不使用共享资源。 共享资源然后可以用于周期X上的操作的第一方面，然后用于周期X + N处的操作的第二方面。 可以根据实施例重新安排第二操作。
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8.发明申请公开(公告)号：US20130132760A1
公开(公告)日：2013-05-23
申请号：US13683912
申请日：2012-11-21
IPC分类号： G06F1/12
摘要： A computer implemented method includes identifying in an original circuit output signals that drive domain crossing logic separating a first clock domain from a second clock domain. A revised circuit is formed with a register attached to the domain crossing logic. The register receives an output signal and a synchronization signal that precludes the output signal from transitioning at selected clock cycle intervals.
摘要翻译： 计算机实现的方法包括在原始电路中识别输出驱动将第一时钟域与第二时钟域分离的域交叉逻辑的信号。 修改后的电路形成有附加到域交叉逻辑的寄存器。 寄存器接收输出信号和同步信号，该信号排除了输出信号以选定的时钟周期间隔的转变。
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公开(公告)号：US20020178203A1
公开(公告)日：2002-11-28
申请号：US10195522
申请日：2002-07-16
发明人： Morten Stribaek , Pascal Paillier
IPC分类号： G06F007/38
CPC分类号： G06F9/30032 , G06F7/5338 , G06F7/5443 , G06F7/724 , G06F7/725 , G06F9/30036 , G06F9/30101 , G06F9/30145
摘要： A multiply unit includes an extended precision accumulator. Microprocessor instructions are provided for manipulating portions of the extended precision accumulator including an instruction to move the contents of a portion of the extended accumulator to a general-purpose register (nullMFLHXUnull) and an instruction to move the contents of a general-purpose register to a portion of the extended accumulator (nullMTLHXnull).
摘要翻译： 乘法单元包括扩展精度累加器。 提供微处理器指令，用于操纵扩展精度累加器的部分，包括将扩展累加器的一部分的内容移动到通用寄存器（“MFLHXU”）的指令以及移动通用寄存器的内容的指令 到扩展累加器的一部分（“MTLHX”）。
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10.发明授权公开(公告)号：US09189412B2
公开(公告)日：2015-11-17
申请号：US13789443
申请日：2013-03-07
发明人： Ranganathan Sudhakar
CPC分类号： G06F12/0875 , G06F7/57 , G06F9/3824 , G06F9/383 , G06F9/3832
摘要： A processor includes a computation engine to produce a computed value for a set of operands. A cache stores the set of operands and the computed value. The cache is configured to selectively identify a match and a miss for a new set of operands. In the event of a match the computed value is supplied by the cache and a computation engine operation is aborted. In the event of a miss a new computed value for the new set of operands is computed by the computation engine and is stored in the cache.
摘要翻译： 处理器包括计算引擎以产生一组操作数的计算值。 高速缓存存储操作数集合和计算值。 缓存被配置为选择性地识别新的操作数集合的匹配和遗漏。 在匹配的情况下，计算值由缓存提供，计算引擎操作中止。 在错过的情况下，新的操作数集合的计算值由计算引擎计算并存储在缓存中。
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