公开(公告)号：US08455298B2

公开(公告)日：2013-06-04

申请号：US12543086

申请日：2009-08-18

Applicant: Mac D. Apodaca ,  Ailian Zhao ,  Jenn C. Chow ,  Thomas Brown ,  Lisa Ceder

Inventor： Mac D. Apodaca ,  Ailian Zhao ,  Jenn C. Chow ,  Thomas Brown ,  Lisa Ceder

IPC: H01L21/06

CPC classification number: H01L27/2409 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/141 ,  H01L45/1683

Abstract: A method for fabricating a memory device includes depositing a phase-change and/or a resistive change material. The memory device is formed photolithographically using sixteen or fewer masks.

Abstract translation: 一种用于制造存储器件的方法，包括沉积相变和/或电阻变化材料。 使用十六个或更少的掩模光刻地形成存储器件。

公开(公告)号：US20100047995A1

公开(公告)日：2010-02-25

申请号：US12543086

申请日：2009-08-18

Applicant: Mac D. Apodaca ,  Ailian Zhao ,  Jenn C. Chow ,  Thomas Brown ,  Lisa Ceder

Inventor： Mac D. Apodaca ,  Ailian Zhao ,  Jenn C. Chow ,  Thomas Brown ,  Lisa Ceder

IPC: H01L21/768

CPC classification number: H01L27/2409 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/141 ,  H01L45/1683

Abstract: A method for fabricating a memory device includes depositing a phase-change and/or a resistive change material. The memory device is formed photolithographically using sixteen or fewer masks.

Abstract translation: 一种用于制造存储器件的方法，包括沉积相变和/或电阻变化材料。 使用十六个或更少的掩模光刻地形成存储器件。

公开(公告)号：US20100096610A1

公开(公告)日：2010-04-22

申请号：US12581555

申请日：2009-10-19

Applicant: Hsingya A. Wang ,  Daniel R. Shepard ,  Mac D. Apodaca ,  Ailian Zhao

Inventor： Hsingya A. Wang ,  Daniel R. Shepard ,  Mac D. Apodaca ,  Ailian Zhao

IPC: H01L47/00 ,  H01L21/06

CPC classification number: H01L27/2409 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1683

Abstract: A memory cell includes a current-steering device, a phase-change material disposed thereover, and a heating element and/or a cooling element.

Abstract translation: 存储单元包括电流转向装置，设置在其上的相变材料和加热元件和/或冷却元件。

公开(公告)号：US20140335669A1

公开(公告)日：2014-11-13

申请号：US14306801

申请日：2014-06-17

Applicant: Daniel R. Shepard ,  Mac D. Apodaca ,  Thomas Michael Trent ,  James Juen Hsu

Inventor： Daniel R. Shepard ,  Mac D. Apodaca ,  Thomas Michael Trent ,  James Juen Hsu

IPC: H01L27/24 ,  H01L45/00 ,  H01L21/8238

CPC classification number: H01L27/2463 ,  H01L21/8238 ,  H01L27/04 ,  H01L27/1021 ,  H01L27/2409 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/14 ,  H01L45/141 ,  H01L45/144 ,  H01L45/16 ,  H01L45/1683

Abstract: The present invention is a method of incorporating a non-volatile memory into a CMOS process that requires four or fewer masks and limited additional processing steps. The present invention is an epi-silicon or poly-silicon process sequence that is introduced into a standard CMOS process (i) after the MOS transistors' gate oxide is formed and the gate poly-silicon is deposited (thereby protecting the delicate surface areas of the MOS transistors) and (ii) before the salicided contacts to those MOS transistors are formed (thereby performing any newly introduced steps having an elevated temperature, such as any epi-silicon or poly-silicon deposition for the formation of diodes, prior to the formation of that salicide). A 4F2 memory array is achieved with a diode matrix wherein the diodes are formed in the vertical orientation.

公开(公告)号：US09054031B2

公开(公告)日：2015-06-09

申请号：US14306801

申请日：2014-06-17

Applicant: Daniel R. Shepard ,  Mac D. Apodaca ,  Thomas Michael Trent ,  James Juen Hsu

Inventor： Daniel R. Shepard ,  Mac D. Apodaca ,  Thomas Michael Trent ,  James Juen Hsu

IPC: H01L27/24 ,  H01L45/00 ,  H01L21/8238 ,  H01L27/04 ,  H01L27/102

CPC classification number: H01L27/2463 ,  H01L21/8238 ,  H01L27/04 ,  H01L27/1021 ,  H01L27/2409 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/14 ,  H01L45/141 ,  H01L45/144 ,  H01L45/16 ,  H01L45/1683

Abstract: The present invention is a method of incorporating a non-volatile memory into a CMOS process that requires four or fewer masks and limited additional processing steps. The present invention is an epi-silicon or poly-silicon process sequence that is introduced into a standard CMOS process (i) after the MOS transistors' gate oxide is formed and the gate poly-silicon is deposited (thereby protecting the delicate surface areas of the MOS transistors) and (ii) before the salicided contacts to those MOS transistors are formed (thereby performing any newly introduced steps having an elevated temperature, such as any epi-silicon or poly-silicon deposition for the formation of diodes, prior to the formation of that salicide). A 4F2 memory array is achieved with a diode matrix wherein the diodes are formed in the vertical orientation.

Abstract translation: 本发明是将非易失性存储器并入到需要四个或更少的掩模和有限的附加处理步骤的CMOS工艺中的方法。 本发明是在形成MOS晶体管的栅极氧化物并且沉积栅极多晶硅之后引入到标准CMOS工艺（i）中的外延硅或多晶硅工艺序列（从而保护晶体管的精细表面积 MOS晶体管）和（ii）在形成与这些MOS晶体管的接触水银之前（因此，在进行二氧化硅的形成之前，执行任何新引入的具有升高温度的步骤，例如用于形成二极管的任何外延硅或多晶硅沉积） 形成那个自杀者）。 使用二极管矩阵实现4F2存储器阵列，其中二极管以垂直取向形成。