公开(公告)号：US5982225A

公开(公告)日：1999-11-09

申请号：US907149

申请日：1997-08-06

申请人： Timothy E. Forhan ,  Terence B. Hook ,  Steven W. Mittl ,  Edward J. Nowak ,  Madhu Sayala ,  Ronald A. Warren

发明人： Timothy E. Forhan ,  Terence B. Hook ,  Steven W. Mittl ,  Edward J. Nowak ,  Madhu Sayala ,  Ronald A. Warren

IPC分类号： H03K17/10 ,  H03K17/14 ,  H03K17/06 ,  H03K17/687

CPC分类号： H03K17/102 ,  H03K17/145

摘要： A circuit actively monitors and measures the amount of MOS device degradation due to, for example, the hot electron effect, and makes compensatory adjustments to device voltage levels or clock speed to maintain desired levels of functionality and performance. Monitoring can be done separately for NFET and PFET devices to selectively adjust for different degradation rates between the two. In operation, the monitor circuit compares the performance of a stressed device to a reference device, that is, an unstressed device which has not been degraded by the hot-electron effect. The monitor circuit outputs a signal indicating the amount of device degradation. This signal is used to adjust the supply voltage to that device or to the chip or otherwise compensate for the degradation. The monitor circuit can be formed on-chip or off-chip.

摘要翻译： 电路主动监测和测量由于例如热电子效应引起的MOS器件退化的量，并且对器件电压电平或时钟速度进行补偿性调整以维持期望的功能和性能水平。 可以分别对NFET和PFET器件进行监控，以选择性地调整两者之间的不同降解率。 在操作中，监视电路将应力装置的性能与参考装置进行比较，即，未受热电子效应劣化的未受应力的装置。 监视电路输出指示设备劣化量的信号。 该信号用于调整该器件或芯片的电源电压或以其他方式补偿降级。 监控电路可以片上或片外形成。

公开(公告)号：US08803537B2

公开(公告)日：2014-08-12

申请号：US13030658

申请日：2011-02-18

申请人： Pat Buehler ,  Sumanth Varma Lokanath ,  Madhu Sayala ,  Christinia Snider ,  Jim Sorensen ,  Paul Wolffersdorff

发明人： Pat Buehler ,  Sumanth Varma Lokanath ,  Madhu Sayala ,  Christinia Snider ,  Jim Sorensen ,  Paul Wolffersdorff

IPC分类号： G01R31/00

CPC分类号： H02S50/10

摘要： A method for conditioning a photovoltaic module for testing includes setting an effective irradiance of a continuous light source at a target plane, configuring a test photovoltaic module to operate at a substantially maximum power point configuration, positioning the test photovoltaic module adjacent to the target plane, and configuring the test photovoltaic module for testing by removing the light source, cooling the test module to a testing temperature, and reversing the substantially maximum power point configuration.

摘要翻译： 用于调节用于测试的光伏模块的方法包括将连续光源的有效辐照度设置在目标平面上，配置测试光伏模块以基本上最大功率点配置操作，将测试光伏模块定位成与目标平面相邻， 并通过去除光源来配置测试光伏模块进行测试，将测试模块冷却到测试温度，并反转基本上最大功率点配置。

公开(公告)号：US20110204909A1

公开(公告)日：2011-08-25

申请号：US13030658

申请日：2011-02-18

申请人： Pat Buehler ,  Sumanth Varma Lokanath ,  Madhu Sayala ,  Christinia Snider ,  Jim Sorensen ,  Paul Wolffersdorff

发明人： Pat Buehler ,  Sumanth Varma Lokanath ,  Madhu Sayala ,  Christinia Snider ,  Jim Sorensen ,  Paul Wolffersdorff

IPC分类号： G01R31/00

CPC分类号： H02S50/10

摘要： A method for conditioning a photovoltaic module for testing includes setting an effective irradiance of a continuous light source at a target plane, configuring a test photovoltaic module to operate at a substantially maximum power point configuration, positioning the test photovoltaic module adjacent to the target plane, and configuring the test photovoltaic module for testing by removing the light source, cooling the test module to a testing temperature, and reversing the substantially maximum power point configuration.

摘要翻译： 用于调节用于测试的光伏模块的方法包括将连续光源的有效辐照度设置在目标平面上，配置测试光伏模块以基本上最大功率点配置操作，将测试光伏模块定位成与目标平面相邻， 并通过去除光源来配置测试光伏模块进行测试，将测试模块冷却到测试温度，并反转基本上最大功率点配置。

公开(公告)号：US07085977B2

公开(公告)日：2006-08-01

申请号：US10011220

申请日：2001-10-25

申请人： Andrew Marshall ,  C. Keith Burgess ,  Charles D. Weinberger ,  Madhu Sayala

发明人： Andrew Marshall ,  C. Keith Burgess ,  Charles D. Weinberger ,  Madhu Sayala

IPC分类号： G01R31/28 ,  G01R31/02

CPC分类号： G01R31/2884

摘要： In one aspect of the invention, a semiconductor die includes a plurality of resistive elements operable to receive a voltage differential between at least two of the resistive elements. The semiconductor die also includes a test circuit coupled to at least three tap points along the resistive elements. The test circuit is operable to measure a voltage at at least two of the tap points. A difference in the voltages between the at least two tap points is proportional to a resistance of the one or more resistive elements between the at least two tap points.