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公开(公告)号：US5982225A
公开(公告)日：1999-11-09
申请号：US907149
申请日：1997-08-06
申请人： Timothy E. Forhan , Terence B. Hook , Steven W. Mittl , Edward J. Nowak , Madhu Sayala , Ronald A. Warren
发明人： Timothy E. Forhan , Terence B. Hook , Steven W. Mittl , Edward J. Nowak , Madhu Sayala , Ronald A. Warren
IPC分类号： H03K17/10 , H03K17/14 , H03K17/06 , H03K17/687
CPC分类号： H03K17/102 , H03K17/145
摘要： A circuit actively monitors and measures the amount of MOS device degradation due to, for example, the hot electron effect, and makes compensatory adjustments to device voltage levels or clock speed to maintain desired levels of functionality and performance. Monitoring can be done separately for NFET and PFET devices to selectively adjust for different degradation rates between the two. In operation, the monitor circuit compares the performance of a stressed device to a reference device, that is, an unstressed device which has not been degraded by the hot-electron effect. The monitor circuit outputs a signal indicating the amount of device degradation. This signal is used to adjust the supply voltage to that device or to the chip or otherwise compensate for the degradation. The monitor circuit can be formed on-chip or off-chip.
摘要翻译： 电路主动监测和测量由于例如热电子效应引起的MOS器件退化的量，并且对器件电压电平或时钟速度进行补偿性调整以维持期望的功能和性能水平。 可以分别对NFET和PFET器件进行监控，以选择性地调整两者之间的不同降解率。 在操作中，监视电路将应力装置的性能与参考装置进行比较，即，未受热电子效应劣化的未受应力的装置。 监视电路输出指示设备劣化量的信号。 该信号用于调整该器件或芯片的电源电压或以其他方式补偿降级。 监控电路可以片上或片外形成。
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2.发明授权Method to calculate hot-electron test voltage differential for assessing microprocessor reliability 失效计算热电子测试电压差的方法来评估微处理器的可靠性
公开(公告)号：US5634001A
公开(公告)日：1997-05-27
申请号：US474441
申请日：1995-06-07
CPC分类号： G06F11/24 , G01R31/3004 , G06F11/261
摘要： A method and system are provided for determining a guard band voltage differential for testing a microprocessor. The guard band voltage differential approximates microprocessor circuit propagation delay degradation expected to occur over the life of the microprocessor. The system and method are performed by first partitioning a microprocessor into a plurality of cones of n circuit level models. Timing simulation data and degradation data are created to represent, respectively, the timing operation for each of the circuit level model circuit paths, and the hot-electron effects on propagation delay degradation for each of the circuit level models. Propagation delay is identified using this data for each of the circuit paths for the circuit level models at times corresponding to the beginning-of-life and end-of-life of the microprocessor. Propagation delay degradation is calculated as the difference between the propagation delay at these times. A range of applied power supply voltages necessary to successfully perform a functional test of the microprocessor over a corresponding range of microprocessor cycle times is experimentally determined. Based on the calculated propagation delay degradation and on the range of applied power supply voltages, a guard band voltage differential for testing the microprocessor is determined.
摘要翻译： 提供了一种用于确定用于测试微处理器的保护带电压差的方法和系统。 保护带电压差近似微处理器在微处理器使用寿命期间预期发生的微处理器电路传播延迟劣化。 该系统和方法通过首先将微处理器划分成n个电路级模型的多个锥来执行。 创建定时仿真数据和劣化数据以分别表示每个电路级模型电路路径的定时操作，以及针对每个电路级模型的热电子对传播延迟劣化的影响。 在与微处理器的使用寿命和使用寿命相对应的时间，针对电路电平模型的每个电路路径，使用该数据来识别传播延迟。 传播延迟退化计算为这些时间的传播延迟之间的差异。 在微处理器循环时间的相应范围内成功执行微处理器的功能测试所需的一系列应用电源电压是实验确定的。 基于所计算的传播延迟劣化和所施加的电源电压的范围，确定用于测试微处理器的保护带电压差。
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公开(公告)号：US06252275B1
公开(公告)日：2001-06-26
申请号：US09226677
申请日：1999-01-07
申请人： John M. Aitken , Steven W. Mittl , Alvin W. Strong
发明人： John M. Aitken , Steven W. Mittl , Alvin W. Strong
IPC分类号： H01L29788
CPC分类号： H01L29/66825 , H01L21/28273 , H01L21/84 , H01L27/1203 , H01L29/7881
摘要： A non-volatile random access memory (NVRAM) structure comprising an injector element in a single crystal silicon substrate; an insulator layer over the substrate; a silicon-on-insulator (SOI) layer over the insulator layer; and a sensing element in the SOI layer overlying the injector element. The NVRAM structure may further comprise a gate above the SOI layer, a floating gate in the insulator layer, or both.
摘要翻译： 一种非易失性随机存取存储器（NVRAM）结构，其包括在单晶硅衬底中的注入元件; 衬底上的绝缘体层; 在绝缘体层上的绝缘体上硅（SOI）层; 以及覆盖注射器元件的SOI层中的感测元件。 NVRAM结构还可以包括在SOI层上方的栅极，绝缘体层中的浮动栅极或两者。
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4.发明授权Measuring bias temperature instability induced ring oscillator frequency degradation 失效测量偏置温度不稳定引起的环形振荡器频率降低公开(公告)号：US08587383B2
公开(公告)日：2013-11-19
申请号：US13313416
申请日：2011-12-07
IPC分类号： G01R23/00 , G01R31/3187 , H03K3/03
CPC分类号： G01R31/2824 , H03K3/0315
摘要： A method establishes an initial voltage in a ring oscillator and a logic circuit of an integrated circuit device. Following this, the method enables the operating state of the ring oscillator. After enabling the operating state of the ring oscillator, the method steps up to a stressing voltage in the ring oscillator. The initial voltage is approximately one-half the stressing voltage. The stressing voltage creates operating-level stress within the ring oscillator. The method measures the operating-level frequency within the ring oscillator using an oscilloscope (after stepping up to the stressing voltage).
摘要翻译： 一种方法在环形振荡器和集成电路器件的逻辑电路中建立初始电压。 此后，该方法启用环形振荡器的工作状态。 在启用环形振荡器的工作状态之后，该方法在环形振荡器中达到应力电压。 初始电压约为应力电压的一半。 应力电压在环形振荡器内产生工作电平应力。 该方法使用示波器测量环形振荡器内的工作电平频率（升压到应力电压之后）。
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5.发明申请CORRECTION FOR STRESS INDUCED LEAKAGE CURRENT IN DIELECTRIC RELIABILITY EVALUATIONS 有权电介质可靠性评估中应力诱导漏电流的校正公开(公告)号：US20120303303A1
公开(公告)日：2012-11-29
申请号：US13117819
申请日：2011-05-27
申请人： Steven W. Mittl , Ernest Y. Wu
发明人： Steven W. Mittl , Ernest Y. Wu
IPC分类号： G06F19/00
CPC分类号： G01R31/12 , G01R31/26 , G01R31/2621 , G01R31/2642 , G06F19/00
摘要： Methods, apparatus, and computer program products for evaluating current transients measured during an electrical stress evaluation of a dielectric layer in a semiconductor device. Measured current transients are fit to an equation representing a time dependence for stress induced leakage currents. The measured current transients are corrected based upon stress currents computed from the equation to define corrected current transients.
摘要翻译： 用于评估在半导体器件中的电介质层的电应力评估期间测量的电流瞬变的方法，装置和计算机程序产品。 测量的电流瞬变适合于表示应力诱发漏电流的时间依赖性的方程式。 测量的电流瞬变根据从等式计算的应力电流进行校正，以定义校正的电流瞬变。
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公开(公告)号：US06307250B1
公开(公告)日：2001-10-23
申请号：US08625327
申请日：1996-04-01
申请人： Byron L. Krauter , Chung H. Lam , Linda A. Miller , Steven W. Mittl , Robert F. Sechler , Scott R. Stiffler , Donald L. Thompson
发明人： Byron L. Krauter , Chung H. Lam , Linda A. Miller , Steven W. Mittl , Robert F. Sechler , Scott R. Stiffler , Donald L. Thompson
IPC分类号： H01L2900
CPC分类号： H01L27/0805 , H03K17/22 , Y10T307/852
摘要： An electronic switch circuit switches out bad decoupling capacitors on a high speed integrated circuit chip. The circuit comprises a control device that operates in the subthreshold or off device state to detect leakage in a decoupling capacitor. This control device operates in a low impedance state if the capacitor is good and in a high impedance sate if the capacitor is bad. A feedback circuit is connected from an internal node of the capacitor to a gate of the control device so that once a state of the capacitor is detected it can be stored on the gate of the control device. A single external signal source shared by a group of capacitors activates the control device to detect leakage in the capacitor. The circuit operates to switch out capacitors that fail during normal operation.
摘要翻译： 电子开关电路在高速集成电路芯片上切断不良去耦电容。 该电路包括一个在亚阈值或者关断器件状态下操作以检测去耦电容器中的泄漏的控制装置。 如果电容器良好，则该控制装置工作在低阻抗状态，如果电容器坏，则其工作在高阻抗状态。 反馈电路从电容器的内部节点连接到控制装置的栅极，使得一旦电容器的状态被检测到，就可将其存储在控制装置的栅极上。 由一组电容器共享的单个外部信号源激活控制装置以检测电容器中的泄漏。 该电路用于切换在正常操作期间失败的电容器。
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7.发明授权Correction for stress induced leakage current in dielectric reliability evaluations 有权电介质可靠性评估中应力诱发漏电流的校正公开(公告)号：US08937487B2
公开(公告)日：2015-01-20
申请号：US13117819
申请日：2011-05-27
申请人： Steven W. Mittl , Ernest Y. Yu
发明人： Steven W. Mittl , Ernest Y. Yu
CPC分类号： G01R31/12 , G01R31/26 , G01R31/2621 , G01R31/2642 , G06F19/00
摘要： Methods, apparatus, and computer program products for evaluating current transients measured during an electrical stress evaluation of a dielectric layer in a semiconductor device. Measured current transients are fit to an equation representing a time dependence for stress induced leakage currents. The measured current transients are corrected based upon stress currents computed from the equation to define corrected current transients.
摘要翻译： 用于评估在半导体器件中的电介质层的电应力评估期间测量的电流瞬变的方法，装置和计算机程序产品。 测量的电流瞬变适合于表示应力诱发漏电流的时间依赖性的方程式。 测量的电流瞬变根据从等式计算的应力电流进行校正，以定义校正的电流瞬变。
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8.发明申请MEASURING BIAS TEMPERATURE INSTABILITY INDUCED RING OSCILLATOR FREQUENCY DEGRADATION 失效测量偏温度不稳定性感应振荡器频率降低公开(公告)号：US20130147562A1
公开(公告)日：2013-06-13
申请号：US13313416
申请日：2011-12-07
IPC分类号： G01R23/00
CPC分类号： G01R31/2824 , H03K3/0315
摘要： A method establishes an initial voltage in a ring oscillator and a logic circuit of an integrated circuit device. Following this, the method enables the operating state of the ring oscillator. After enabling the operating state of the ring oscillator, the method steps up to a stressing voltage in the ring oscillator. The initial voltage is approximately one-half the stressing voltage. The stressing voltage creates operating-level stress within the ring oscillator. The method measures the operating-level frequency within the ring oscillator using an oscilloscope (after stepping up to the stressing voltage).
摘要翻译： 一种方法在环形振荡器和集成电路器件的逻辑电路中建立初始电压。 此后，该方法启用环形振荡器的工作状态。 在启用环形振荡器的工作状态之后，该方法在环形振荡器中达到应力电压。 初始电压约为应力电压的一半。 应力电压在环形振荡器内产生工作电平应力。 该方法使用示波器测量环形振荡器内的工作电平频率（升压到应力电压之后）。
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公开(公告)号：US06770501B2
公开(公告)日：2004-08-03
申请号：US10277835
申请日：2002-10-23
IPC分类号： H01L213205
CPC分类号： H01L21/76224 , H01L21/3003 , H01L21/823481
摘要： Semiconductor structures are provided with on-board deuterium reservoirs or with deuterium ingress paths which allow for diffusion of deuterium to semiconductor device regions for passivation purposes. The on-board deuterium reservoirs are in the form of plugs which extend through an insulating layer and a deuterium barrier layer to the semiconductor substrate, and are preferably positioned in contact with a shallow trench oxide which will allow diffusion of deuterium to the semiconductor devices. The deuterium ingress paths extend through thin film layers from the top or through the silicon substrate. The latter include shallow trench isolations formed in a semiconductor substrate which are adjacent and connected to semiconductor devices formed in the semiconductor substrate, and where the back portion of the semiconductor substrate has been polished or ground down to the bottom of the shallow trench isolation, thereby allowing deuterium, during an anneal, to diffuse from the back through the shallow trench isolation to the semiconductor devices in the semiconductor substrate.
摘要翻译： 半导体结构设置有板上氘储层或氘入口路径，其允许氘扩散到半导体器件区域用于钝化目的。 板上氘储存器是插塞的形式，其延伸穿过绝缘层和氘屏障层到半导体衬底，并且优选地定位成与允许氘扩散到半导体器件的浅沟槽氧化物接触。 氘入口路径从顶部或穿过硅衬底延伸穿过薄膜层。 后者包括形成在半导体衬底中的与沟道半导体衬底中形成的半导体器件相邻并连接的浅沟槽隔离，并且其中半导体衬底的后部已经被抛光或者被研磨到浅沟槽隔离的底部，由此 允许在退火期间的氘从后面通过浅沟槽隔离扩散到半导体衬底中的半导体器件。
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公开(公告)号：US06521977B1
公开(公告)日：2003-02-18
申请号：US09489277
申请日：2000-01-21
IPC分类号： H01L2358
CPC分类号： H01L21/76224 , H01L21/3003 , H01L21/823481
摘要： Semiconductor structures are provided with on-board deuterium reservoirs or with deuterium ingress paths which allow for diffusion of deuterium to semiconductor device regions for passivation purposes. The on-board deuterium reservoirs are in the form of plugs which extend through an insulating layer and a deuterium barrier layer to the semiconductor substrate, and are preferably positioned in contact with a shallow trench oxide which will allow diffusion of deuterium to the semiconductor devices. The deuterium ingress paths extend through thin film layers from the top or through the silicon substrate. The latter include shallow trench isolations formed in a semiconductor substrate which are adjacent and connected to semiconductor devices formed in the semiconductor substrate, and where the back portion of the semiconductor substrate has been polished or ground down to the bottom of the shallow trench isolation, thereby allowing deuterium, during an anneal, to diffuse from the back through the shallow trench isolation to the semiconductor devices in the semiconductor substrate.
摘要翻译： 半导体结构设置有板上氘储层或氘入口路径，其允许氘扩散到半导体器件区域用于钝化目的。 板上氘储存器是插塞的形式，其延伸穿过绝缘层和氘屏障层到半导体衬底，并且优选地定位成与允许氘扩散到半导体器件的浅沟槽氧化物接触。 氘入口路径从顶部或穿过硅衬底延伸穿过薄膜层。 后者包括形成在半导体衬底中的与沟道半导体衬底中形成的半导体器件相邻并连接的浅沟槽隔离，并且其中半导体衬底的后部已经被抛光或者被研磨到浅沟槽隔离的底部，由此 允许在退火期间的氘从后面通过浅沟槽隔离扩散到半导体衬底中的半导体器件。
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