公开(公告)号：US6157603A

公开(公告)日：2000-12-05

申请号：US105170

申请日：1998-06-26

申请人： Mamiko Okubo ,  Hiroshi Shimada

发明人： Mamiko Okubo ,  Hiroshi Shimada

IPC分类号： G11B20/10 ,  G11B7/005 ,  G11B19/26 ,  G11B20/14 ,  H03L7/08 ,  G11B7/00

CPC分类号： H03L7/0805 ,  G11B19/26 ,  G11B20/14 ,  G11B7/005 ,  H03L7/0807

摘要： A data slice circuit which generates a EFM signal from a RF signal includes a clock signal generator circuit for generating a clock signal not synchronized with the EFM signal. The data slice circuit divides a clock signal not synchronized with the EFM signal, by a divider, to generate a clock signal for counting. The clock signal for counting is inputted as a clock into an up/down counter. Up/down count control of the up/down counter is performed on the basis of an output from a comparator. The comparator compares the RF signal with a reference voltage and outputs data "1" or "0" in accordance with the comparison result. A count output of the up/down counter is converted into an analog voltage by a digital/analog converter and is supplied as a reference voltage to the comparator.

摘要翻译： 从RF信号生成EFM信号的数据限幅电路包括用于产生与EFM信号不同步的时钟信号的时钟信号发生器电路。 数据切片电路通过分频器将与EFM信号不同步的时钟信号分频，以产生用于计数的时钟信号。 用于计数的时钟信号作为时钟输入到向上/向下计数器。 基于比较器的输出执行向上/向下计数器的向上/向下计数控制。 比较器将RF信号与参考电压进行比较，并根据比较结果输出数据“1”或“0”。 上/下计数器的计数输出由数/模转换器转换为模拟电压，并作为参考电压提供给比较器。

公开(公告)号：US6064271A

公开(公告)日：2000-05-16

申请号：US104995

申请日：1998-06-26

申请人： Mamiko Okubo ,  Hiroshi Shimada

发明人： Mamiko Okubo ,  Hiroshi Shimada

IPC分类号： G11B20/14 ,  H03L7/081 ,  H03L7/099 ,  H03L7/00

CPC分类号： H03L7/0805 ,  G11B20/1403 ,  H03L7/0812 ,  H03L7/0997

摘要： In a disc reproducing apparatus using a VCO (voltage controlled oscillator) circuit, the VCO circuit includes a first delay cell array having gates supplied with a first control voltage DCV, a ring oscillator including a second delay cell array having gates supplied with a second control voltage Vin, and a switch for selecting the number of delay cells from the second delay cell array. The oscillation frequency of the ring oscillator is determined by a time delay of the second delay cell array. When the second control voltage Vin having the same value as the first control voltage DCV is inputted to the gates of the delay cells of the second delay cell array, the ring oscillator oscillates with a frequency determined by the ratio of the number of the delay cells of the first delay cell array to number of the delay cells of the second delay cell array. By operating the selection switch to change the number of delay cells constituting the second delay cell array, the voltage controlled oscillator (VCO) circuit can generates a signal of an oscillation frequency of a frequency division ratio other than 1/2.sup.n, by using at least one reference clock.

摘要翻译： 在使用VCO（压控振荡器）电路的盘再现装置中，VCO电路包括具有提供有第一控制电压DCV的栅极的第一延迟单元阵列，包括第二延迟单元阵列的环形振荡器，第二延迟单元阵列具有提供有第二控制 电压Vin和用​​于从第二延迟单元阵列中选择延迟单元的数量的开关。 环形振荡器的振荡频率由第二延迟单元阵列的时间延迟确定。 当具有与第一控制电压DCV相同值的第二控制电压Vin被输入到第二延迟单元阵列的延迟单元的栅极时，环形振荡器以由延迟单元的数量的比率确定的频率振荡 的第一延迟单元阵列到第二延迟单元阵列的延迟单元的数目。 通过操作选择开关来改变构成第二延迟单元阵列的延迟单元的数量，压控振荡器（VCO）电路可以产生除+ E之外的分频比的振荡频率的信号，f 1/2 + EE n，通过使用至少一个参考时钟。