公开(公告)号：US09063518B2

公开(公告)日：2015-06-23

申请号：US13702159

申请日：2011-06-05

Applicant: Dariusz Koscielnik ,  Marek Miskowicz

Inventor： Dariusz Koscielnik ,  Marek Miskowicz

IPC: H03M1/50 ,  G04F10/00

CPC classification number: G04F10/00 ,  G04F10/005

Abstract: The solution according to the invention consisting in conversion of a time interval to a digital word of a number of bits equal to n by the use of the array (A) of binary-scaled capacitors (Cn-1, . . . , C0) is characterized in that the time interval whose both start and end are detected by the control module (CM) is first mapped to a portion of electric charge delivered by the current source (I) and successively accumulated in the capacitors ((Cn-1, . . . , C0)) in the order of decreasing capacitances starting from the capacitor (Cn-1) having the highest capacitance value in the array, and when the control module (CM) detects the end of the time interval, the charge accumulated in the capacitor (Cx) charged recently is successively transferred by the use of the current source (I) to the capacitors of lower capacitance values. The process of charge transfer is controlled by the control module (CM) on the basis of the output signals of the comparators (K1) and (K2) without the use of a clock while the value one is assigned to these bits (bn-1, . . . , b0) in the digital output word that correspond to the capacitors (Cn-1, . . . , C0) on which the reference voltage (UL) of a desired value has been obtained, and the value zero is assigned to the other bits.

Abstract translation: 根据本发明的解决方案包括通过使用二进制比例电容器（Cn-1，...，C0）的阵列（A）将时间间隔转换成等于n的位数的数字字， 其特征在于，由控制模块（CM）检测出开始和结束的时间间隔首先映射到由电流源（I）传送的电荷的一部分，并依次累积在电容器（（Cn-1， ...，C0）），从阵列中具有最高电容值的电容器（Cn-1）开始降低电容的顺序，并且当控制模块（CM）检测到时间间隔的结束时，电荷累积 在最近充电的电容器（Cx）中，通过使用电流源（I）连续传送到具有较低电容值的电容器。 基于比较器（K1）和（K2）的输出信号，电荷转移的过程由控制模块（CM）控制，而不使用时钟，而值1分配给这些位（bn-1 ，...，b0）对应于其上已获得期望值的参考电压（UL）的电容器（Cn-1，...，C0），并且分配值零 到其他位。

公开(公告)号：US20130214960A1

公开(公告)日：2013-08-22

申请号：US13755312

申请日：2013-01-31

Applicant: Dariusz KOSCIELNIK ,  Marek MISKOWICZ

Inventor： Dariusz KOSCIELNIK ,  Marek MISKOWICZ

IPC: H03M1/12

CPC classification number: H03M1/12 ,  G04F10/005 ,  G04F10/105

Abstract: Method and apparatus for accumulation of electric charge delivered to the charge input (InQ) in the sampling capacitor (Cn) and in realization of the process of charge redistribution in the array of redistribution (A) by changing states of signals from relevant control outputs and in assignment of relevant values to bits in the digital word by means of the control module (CM). Method is characterized in that after detection of the beginning of the next gate signal (Gx+1), the charge is accumulated in the additional sampling capacitor (CnA), and then the process of charge redistribution is realized and relevant values are assigned to bits of the digital word. When the beginning of the subsequent gate signal (Gx+2) is detected, the next cycle begins and electric charge is accumulated in the sampling capacitor (Cn) again.

Abstract translation: 用于累积传送到采样电容器（Cn）中的电荷输入（InQ）的电荷的方法和装置，以及通过改变来自相关控制输出的信号的状态来实现再分配阵列（A）中的电荷再分配的过程，以及 通过控制模块（CM）将相关值分配给数字字中的位。 方法的特征在于，在检测到下一个栅极信号（Gx + 1）的开始后，电荷累积在附加采样电容器（CnA）中，然后实现电荷再分配的处理，并将相关值分配给位 的数字词。 当检测到后续门信号（Gx + 2）的开始时，下一个周期开始，电荷再次累积在采样电容器（Cn）中。

公开(公告)号：US09137040B2

公开(公告)日：2015-09-15

申请号：US13256285

申请日：2010-03-13

Applicant: Marek Miskowicz

Inventor： Marek Miskowicz

IPC: H04L12/28 ,  H04L12/413

CPC classification number: H04L12/413

Abstract: Method of controlling the access of devices to the communication media in distributed networks of CSMA (Carrier Sense Multiple Access) type is characterized by that each time before the packet transmission attempt, if the communication medium is detected to be idle, the prespecified fixed time interval equal to the minimum interpacket space is timed out during which the random numbers of time slots defining the order of media access are selected from the fixed number of slots of equal width using the pseudorandom number generator in every node where the probability of a selection of a particular slot is geometric with a characteristic parameter defined as the ratio of the probability of a selection of a given slot to the probability of a selection of the next slot, which changes from zero to one as a discrete function of the state of the node's counter, and after that the time interval of random delay corresponding to the selected random is assigned. After the minimum interpacket space the phase of known sequential priority access is started and subsequently, the random delay assigned previously is timed out and at the same time the state of the communication medium is sensed again, and if the communication medium is still sensed idle, it is made available to the node with the lowest number of the slot randomly selected. After completing a given packet reception, the states of the counters in all the nodes in a given network segment are increased by the increment defining the number of expected packets that will be generated in a result of the reception of the transmitted packet reduced by one, and next, the cycle is repeated. During the data packet transmission the collisions are detected optionally in the communication medium by the collision detectors, and next, the states of the counters are changed in the nodes with the use of the corresponding control signals obtained from the collision detectors, and in case the communication medium is detected to be idle after the time equal to the sum of the minimum interpacket space and the time delay defined by the prespecified fixed maximum number of slots, the states of the counters in all the nodes in a given network segment are decreased by one with the use of the control signals obtained from the communication medium state detectors.

公开(公告)号：US08878714B2

公开(公告)日：2014-11-04

申请号：US13755002

申请日：2013-01-31

Applicant: Dariusz Koscielnik ,  Marek Miskowicz

Inventor： Dariusz Koscielnik ,  Marek Miskowicz

IPC: H03M1/34 ,  H03M1/12 ,  H03M1/46

CPC classification number: H03M1/12 ,  H03M1/1245 ,  H03M1/125 ,  H03M1/466

Abstract: Method and apparatus for mapping the converted voltage value by electric charge value proportional to the converted voltage value and in accumulation of charge in the sampling capacitor until the voltage on this capacitor is equal to the converted voltage. Furthermore, realization of the process of that electric charge redistribution in the array of redistribution by changes of states of signals from relevant control outputs and in assignment of relevant values to bits in the digital word by means of the control module. As soon as accumulation of electric charge in the sampling capacitor is terminated, electric charge is accumulated in the additional sampling capacitor then the process of that electric charge redistribution is realized and relevant values are assigned to bits of the digital word. When a trigger signal is detected, next cycle begins and electric charge is accumulated in the sampling capacitor.

Abstract translation: 用于通过与转换的电压值成比例的电荷值和采样电容器中的电荷积累来映射转换的电压值，直到该电容器上的电压等于转换的电压的方法和装置。 此外，通过控制模块通过来自相关控制输出的信号的状态的变化以及相关值分配给数字字中的位来实现再分配阵列中的电荷再分配过程。 一旦采样电容器中的电荷累积终止，则在附加采样电容器中累积电荷，则实现该电荷再分配的处理，并将相关值分配给数字字的位。 当检测到触发信号时，下一个周期开始，电荷在采样电容器中累积。

公开(公告)号：US08868812B2

公开(公告)日：2014-10-21

申请号：US13260269

申请日：2010-03-31

Applicant: Marek Miskowicz ,  Dariusz Koscielnik

Inventor： Marek Miskowicz ,  Dariusz Koscielnik

IPC: G06F13/14 ,  G06F13/38

CPC classification number: G06F13/385 ,  Y02D10/14 ,  Y02D10/151

Abstract: A conversion module contains an asynchronous analog-to-digital converter (AADC) with the output signal generated at irregular time intervals, whose output is connected to the input of the buffer memory module (BUF), and the output of the buffer memory module (BUF) is connected through the internal bus (BUS) simultaneously to the source address module (SADR), to the configuration registers module (REG), to the control module of the interface (CM), which the reference generator (RG) is connected to, and to the destination address module (DADR), to the selection register module (SELREG), to the transmitter/receiver module (SDM), and moreover the control inputs/outputs (1, 2, . . . , 8) of the control module (CM) are connected respectively to the asynchronous analog-to-digital converter (AADC), to the buffer memory module (BUF), to the source address module (SADR), to the configuration registers module (REG), to the destination address module (DADR), to the selection register module (SELREG), to the transmitter/receiver module (SDM), and to the clock control module (SCM), and on the other hand, the transmitter/receiver module (SDM) output is connected through the controller (SDD) to the data line (SDA) of the I2C bus whose clock line (SCL) is connected through the other controller (SCD) to the clock control module (SCD) output, and what is more the write control output (9) of the asynchronous analog-to-digital converter (AADC) is connected to the write control input (10) of the buffer memory module (BUF).

Abstract translation: 转换模块包含异步模数转换器（AADC），其输出信号以不规则的时间间隔生成，其输出连接到缓冲存储器模块（BUF）的输入端，缓冲存储器模块 BUF）通过内部总线（BUS）同时连接到源地址模块（SADR），配置寄存器模块（REG）连接到参考发生器（RG）连接的接口（CM）的控制模块 到目的地地址模块（DADR）到选择寄存器模块（SELREG）到发射机/接收机模块（SDM），以及控制输入/输出（1,2，...，8） 控制模块（CM）分别连接到异步模数转换器（AADC），缓冲存储器模块（BUF），源地址模块（SADR），配置寄存器模块（REG），到 目的地址模块（DADR），到选择寄存器模块（SELRE G），发射机/接收机模块（SDM）和时钟控制模块（SCM），另一方面，发射机/接收机模块（SDM）输出通过控制器（SDD）连接到数据线 其时钟线（SCL）通过另一个控制器（SCD）连接到时钟控制模块（SCD）输出的I2C总线的SDA（SDA），以及异步模数转换器 数字转换器（AADC）连接到缓冲存储器模块（BUF）的写入控制输入（10）。

公开(公告)号：US20130222170A1

公开(公告)日：2013-08-29

申请号：US13702159

申请日：2011-06-05

Applicant: Dariusz Koscielnik ,  Marek Miskowicz

Inventor： Dariusz Koscielnik ,  Marek Miskowicz

IPC: G04F10/00

CPC classification number: G04F10/00 ,  G04F10/005

Abstract: The solution according to the invention consisting in conversion of a time interval to a digital word of a number of bits equal to n by the use of the array (A) of binary-scaled capacitors (C.n-1, . . . , C0) is characterized in that the time interval whose both start and end are detected by the control module (CM) is first mapped to a portion of electric charge delivered by the current source (I) and successively accumulated in the capacitors ((Cn-1, . . . , C0)) in the order of decreasing capacitances starting from the capacitor (Cn-1) having the highest capacitance value in the array, and when the control module (CM) detects the end of the time interval, the charge accumulated in the capacitor (Cx) charged recently is successively transferred by the use of the current source (I) to the capacitors of lower capacitance values. The process of charge transfer is controlled by the control module (CM) on the basis of the output signals of the comparators (K1) and (K2) without the use of a clock while the value one is assigned to these bits (bn-1, . . . , b0) in the digital output word that correspond to the capacitors (Cn-1, . . . , C0) on which the reference voltage (UL) of a desired value has been obtained, and the value zero is assigned to the other bits.

Abstract translation: 根据本发明的解决方案包括通过使用二进制比例电容器（Cn-1，...，C0）的阵列（A）将时间间隔转换成等于n的位数的数字字， 其特征在于，由控制模块（CM）检测出开始和结束的时间间隔首先映射到由电流源（I）传送的电荷的一部分，并依次累积在电容器（（Cn-1， ...，C0）），从阵列中具有最高电容值的电容器（Cn-1）开始降低电容的顺序，并且当控制模块（CM）检测到时间间隔的结束时，电荷累积 在最近充电的电容器（Cx）中，通过使用电流源（I）连续传送到具有较低电容值的电容器。 基于比较器（K1）和（K2）的输出信号，电荷转移的过程由控制模块（CM）控制，而不使用时钟，而值1分配给这些位（bn-1 ，...，b0）对应于其上已获得期望值的参考电压（UL）的电容器（Cn-1，...，C0），并且分配值零 到其他位。

公开(公告)号：US20130194123A1

公开(公告)日：2013-08-01

申请号：US13755002

申请日：2013-01-31

Applicant: Dariusz KOSCIELNIK ,  Marek MISKOWICZ

Inventor： Dariusz KOSCIELNIK ,  Marek MISKOWICZ

IPC: H03M1/12

CPC classification number: H03M1/12 ,  H03M1/1245 ,  H03M1/125 ,  H03M1/466

Abstract: Method and apparatus for mapping the converted voltage value by electric charge value proportional to the converted voltage value and in accumulation of charge in the sampling capacitor until the voltage on this capacitor is equal to the converted voltage. Furthermore, realization of the process of that electric charge redistribution in the array of redistribution by changes of states of signals from relevant control outputs and in assignment of relevant values to bits in the digital word by means of the control module. As soon as accumulation of electric charge in the sampling capacitor is terminated, electric charge is accumulated in the additional sampling capacitor then the process of that electric charge redistribution is realized and relevant values are assigned to bits of the digital word. When a trigger signal is detected, next cycle begins and electric charge is accumulated in the sampling capacitor.

Abstract translation: 用于通过与转换的电压值成比例的电荷值和采样电容器中的电荷积累来映射转换的电压值，直到该电容器上的电压等于转换的电压的方法和装置。 此外，通过控制模块通过来自相关控制输出的信号的状态的变化以及相关值分配给数字字中的位来实现再分配阵列中的电荷再分配过程。 一旦采样电容器中的电荷累积终止，则在附加采样电容器中累积电荷，则实现该电荷再分配的处理，并将相关值分配给数字字的位。 当检测到触发信号时，下一个周期开始，电荷在采样电容器中累积。

公开(公告)号：US08922417B2

公开(公告)日：2014-12-30

申请号：US13702181

申请日：2011-06-05

Applicant: Dariusz Koscielnik ,  Marek Miskowicz

Inventor： Dariusz Koscielnik ,  Marek Miskowicz

IPC: H03M1/12 ,  H03M1/46

CPC classification number: H03M1/12 ,  H03M1/466

Abstract: The solution according to the invention consisting in conversion of a portion of electric charge to a digital word of a number of bits equal to n by the use of successive redistribution of charge in the array (A) of binary-scaled capacitors (Cn-1, . . . , Co) is characterized in that charge is first accumulated during the active state of the external gate signal on the gate signal input (InG) in the capacitors (Cn-1, . . . , Co) in the order of decreasing capacitances starting from the capacitor (Cn-1) having the highest capacitance value in the array, and when the active state of the gate signal is terminated, the charge accumulated in the capacitor (Cx) charged recently is successively transferred by the use of the current source (I) to the capacitors of lower capacitance values. The process of charge transfer is controlled by the control module (CM) on the basis of the output signals of the comparators (K1) and (K2) without the use of a clock while the value one is assigned to these bits (bn-1, . . . , b0) in the digital output word that correspond to the capacitors (Cn-1, . . . , Co) on which the reference voltage (UL) of a desired value has been obtained, and the value zero is assigned to the other bits.

Abstract translation: 根据本发明的解决方案包括通过使用二进制比例电容器（Cn-1）的阵列（A）中的电荷的连续重新分配将电荷的一部分转换成等于n的位数的数字字 ，...，Co）的特征在于，在电容器（Cn-1，...，Co）中的栅极信号输入（InG）上的外部栅极信号的有效状态期间，首先累积电荷，顺序为 从阵列中具有最高电容值的电容器（Cn-1）开始降低电容，并且当门信号的有效状态终止时，最近充电的电容器（Cx）中累积的电荷通过使用 电流源（I）到电容器的较低电容值。 基于比较器（K1）和（K2）的输出信号，电荷转移的过程由控制模块（CM）控制，而不使用时钟，而值1分配给这些位（bn-1 ，...，b0）对应于已经获得期望值的参考电压（UL）的电容器（Cn-1，...，Co）的数字输出字，并且分配值零 到其他位。

公开(公告)号：US08830111B2

公开(公告)日：2014-09-09

申请号：US13755390

申请日：2013-01-31

Applicant: Dariusz Koscielnik ,  Marek Miskowicz

Inventor： Dariusz Koscielnik ,  Marek Miskowicz

IPC: H03M1/12 ,  G04F10/00

CPC classification number: G04F10/005

Abstract: Method and apparatus for detecting the beginning and end of a time interval using the control module and in mapping this time interval to a portion of electric charge proportional to this time interval and accumulated in the sampling capacitor and then realizing the process of charge redistribution in the array of redistribution by changing states of signals from relevant control outputs and in assignment of relevant values to bits in the digital word by means of the control module. After detection of the beginning of the next time interval, the charge is accumulated in the additional sampling capacitor and then the process of charge redistribution is realized and relevant values are assigned to bits of the digital word. When the beginning of the subsequent time interval is detected, the next cycle begins and electric charge is accumulated in the sampling capacitor again.

Abstract translation: 使用控制模块检测时间间隔的开始和结束并将该时间间隔映射到与该时间间隔成比例的电荷的一部分并累积在采样电容器中，然后实现电荷再分配过程的方法和装置 通过改变来自相关控制输出的信号的状态以及通过控制模块将相关值分配给数字字中的位的再分配阵列。 在检测到下一个时间间隔的开始之后，电荷累积在附加采样电容器中，然后实现电荷再分配的处理，并且将相关值分配给数字字的位。 当检测到后续时间间隔的开始时，下一个周期开始，并且电荷再次累积在采样电容器中。

公开(公告)号：US20130176157A1

公开(公告)日：2013-07-11

申请号：US13702127

申请日：2011-06-05

Applicant: Dariusz Koscielnik ,  Marek Miskowicz

Inventor： Dariusz Koscielnik ,  Marek Miskowicz

IPC: H03M1/14

CPC classification number: H03M1/14 ,  H03M1/00 ,  H03M1/12 ,  H03M1/125 ,  H03M1/466 ,  H03M1/804

Abstract: The solution according to the invention consisting in conversion of a voltage value to a digital word of a number of bits equal to n is characterized in that the converted voltage value is first mapped to a portion of electric charge accumulated in the sampling capacitor (C-n) during the active state of the signal on the trigger input (InS) and the accumulated charge portion is next successively redistributed by the use of the current source (I) in the array (A) of binary-scaled capacitors (Cn-1, . . . , C0) in the order of decreasing capacitances starting from the capacitor (Cn-1) having the highest capacitance value in the array (A). The process of charge redistribution is controlled by the control module (CM) on the basis of the output signals of the comparators (K1) and (K2) without the use of a clock while the value one is assigned to these bits (bn-1, . . . , b0) in the digital output word that correspond to the capacitors (Cn-1, . . . , C0) on which the reference voltage (UL) of a desired value has been obtained, and the value zero is assigned to the other bits.

Abstract translation: 将根据本发明的将电压值转换为等于n的位数的数字字的根据本发明的解决方案的特征在于，转换的电压值首先映射到在采样电容器（Cn）中累积的电荷的一部分， 在触发输入（InS）的信号的有效状态下，通过使用二进制比例电容器（Cn-1，...）的阵列（A）中的电流源（I），继续重新分配累积电荷部分。 （C0）以从阵列（A）中具有最高电容值的电容器（Cn-1）开始降低电容的顺序。 电荷再分配的过程由控制模块（CM）基于比较器（K1）和（K2）的输出信号控制，而不使用时钟，而值1被分配给这些位（bn-1 ，...，b0）对应于其上已获得期望值的参考电压（UL）的电容器（Cn-1，...，C0），并且分配值零 到其他位。