摘要:
A memory access control system in a vector processing system comprises a memory unit, a memory device, address holding registers, a shift register and data buffer registers. The memory access control system distinguishes each vector data read out from the memory unit based upon the address holding registers by the output of the shift register. The shift register stores vector element numbers indicated by the memory device and transfers same to the data buffer registers. Each number from 0 to n-1, of a vector A composed of n elements a.sub.0, a.sub.1, a.sub.2, . . . a.sub.n-1, is a vector element number and each data, from a.sub.0 to a.sub.n-1, is vector element data.
摘要:
A system for controlling the addition of signed binary numbers represented with N bits, of the 2's complement notation, is disclosed which includes addend and augend sign control circuits, and an adder circuit comprising a carry save adder and a carry proper gate adder. The addend sign control circuit receives an operation command sign signal (B, --B, .vertline.B.vertline. or --.vertline.B.vertline.) for the addend, which designates the addend of the certain type (B, .vertline.B.vertline. or --.vertline.--B.vertline.) to be applied directly to the carry save adder and designates the addend of another type (--B, .vertline.--B.vertline. or --.vertline.B.vertline.) to be applied to the carry save adder through a 1's complementer. The augend sign control circuit functions similarly for the augend being applied to the carry save adder. A corrective number (0, 1 or 2) is applied to the adder circuit which corresponds to neither, one, or both the addend and augend being applied to the adder circuit through their respective 1's complementer.
摘要翻译:公开了一种用于控制由2位补码表示的N位表示的有符号二进制数的加法的系统,其包括加数和加数符号控制电路,以及包括进位存储加法器和进位本门加法器的加法器电路。 加数符号控制电路接收用于加法器的操作命令符号信号(B,-B,| B或-BB),其指定特定类型的加数(B,| B |或 - )直接应用于进位存储加法器,并通过1的补码器指定要应用于进位保存加法器的另一种类型(-B,| -B|或-BB)的加数。 加法符号控制电路的功能类似于加法器应用于进位保存加法器。 校正号码(0,1或2)被施加到加法器电路,对应于加法器电路和加法器电路两者之一,加法器和加法器都不通过其相应的1的补码器。
摘要:
An element damage determination unit calculates a cumulative value of a damage value using a Manson-Coffin law for a plurality of finite elements of a continuum based on a result of a stress/distortion analyzing process, and determines whether or not the cumulative value of the damage value is equal to or exceeds a threshold. A calculation unit obtains first correspondence information indicating the correspondence between the number of cycles of a load and a growth rate of a crack occurring in the continuum based on the determination result. A Manson-Coffin law change unit changes a Manson-Coffin law based on the first correspondence information and second correspondence information indicating the correspondence between an actual measurement value of the number of cycles of a load applied to the continuum and an actual measurement value of the growth rate of a crack occurring in the continuum at that time.
摘要:
An element damage determination unit calculates a cumulative value of a damage value using a Manson-Coffin law for a plurality of finite elements of a continuum based on a result of a stress/distortion analyzing process, and determines whether or not the cumulative value of the damage value is equal to or exceeds a threshold. A calculation unit obtains first correspondence information indicating the correspondence between the number of cycles of a load and a growth rate of a crack occurring in the continuum based on the determination result. A Manson-Coffin law change unit changes a Manson-Coffin law based on the first correspondence information and second correspondence information indicating the correspondence between an actual measurement value of the number of cycles of a load applied to the continuum and an actual measurement value of the growth rate of a crack occurring in the continuum at that time.
摘要:
A list vector control apparatus to be incorporated in a vector processing system includes therein at least a plurality of vector registers. One of the vector registers is operated as a list vector register loading therein list vector elements, while another vector register is operated as a normal vector register to produce list vector data successively with the aid of its address register. The address register is connected to a list vector transfer line for transferring the list vector elements sequentially from the list vector register to produce the desired list vector data.