公开(公告)号：US07813422B2

公开(公告)日：2010-10-12

申请号：US11710212

申请日：2007-02-23

申请人： Matthew E. Cooke ,  Adriel P. Kind ,  Long Ung

发明人： Matthew E. Cooke ,  Adriel P. Kind ,  Long Ung

IPC分类号： H03H7/30 ,  H03H7/40 ,  H03K5/159

CPC分类号： H04L25/03038 ,  H04L25/03057 ,  H04L2025/03687

摘要： In one embodiment, a receiver has an equalizer, a tap-averaging block, a delay buffer, and a filter. The equalizer receives an input signal from upstream processing and generates sets of filter coefficients. Each set of filter coefficients is adaptively generated by 1) filtering the received signal to generate an equalized signal, 2) calculating an error of the equalized signal, and 3) generating a new set of coefficients based on the error of the equalized signal. The sets of filter coefficients are output to the tap-averaging block, which averages groups of the sets of filter coefficients to generate sets of averaged filter coefficients, where each averaged set is output to the filter. The filter receives a time-delayed version of the input signal from the delay buffer and applies the current set of averaged filter coefficients to the time-delayed signal. The filtered signal is then output to downstream processing.

摘要翻译： 在一个实施例中，接收机具有均衡器，抽头平均块，延迟缓冲器和滤波器。 均衡器接收来自上游处理的输入信号并生成滤波器系数集合。 每组滤波器系数通过以下方式自适应地产生：1）对接收信号进行滤波以产生均衡信号，2）计算均衡信号的误差，以及3）基于均衡信号的误差产生一组新的系数。 滤波器系数组被输出到抽头平均块，其平均滤波器系数组的组以生成平均滤波器系数集合，其中每个平均集合被输出到滤波器。 滤波器接收来自延迟缓冲器的输入信号的时间延迟版本，并将当前的平均滤波器系数组应用于时间延迟信号。 然后将经滤波的信号输出到下游处理。

公开(公告)号：US20080205503A1

公开(公告)日：2008-08-28

申请号：US11710212

申请日：2007-02-23

申请人： Matthew E. Cooke ,  Adriel P. Kind ,  Long Ung

发明人： Matthew E. Cooke ,  Adriel P. Kind ,  Long Ung

IPC分类号： H03K5/159

CPC分类号： H04L25/03038 ,  H04L25/03057 ,  H04L2025/03687

摘要： In one embodiment, a receiver has an equalizer, a tap-averaging block, a delay buffer, and a filter. The equalizer receives an input signal from upstream processing and generates sets of filter coefficients. Each set of filter coefficients is adaptively generated by 1) filtering the received signal to generate an equalized signal, 2) calculating an error of the equalized signal, and 3) generating a new set of coefficients based on the error of the equalized signal. The sets of filter coefficients are output to the tap-averaging block, which averages groups of the sets of filter coefficients to generate sets of averaged filter coefficients, where each averaged set is output to the filter. The filter receives a time-delayed version of the input signal from the delay buffer and applies the current set of averaged filter coefficients to the time-delayed signal. The filtered signal is then output to downstream processing.

摘要翻译： 在一个实施例中，接收机具有均衡器，抽头平均块，延迟缓冲器和滤波器。 均衡器接收来自上游处理的输入信号并生成滤波器系数集合。 每组滤波器系数通过以下方式自适应地产生：1）对接收信号进行滤波以产生均衡信号，2）计算均衡信号的误差，以及3）基于均衡信号的误差产生一组新的系数。 滤波器系数的集合被输出到抽头平均块，其平均滤波器系数组的组以生成平均滤波器系数集合，其中每个平均集合被输出到滤波器。 滤波器接收来自延迟缓冲器的输入信号的时间延迟版本，并将当前的平均滤波器系数组应用于时间延迟信号。 然后将经滤波的信号输出到下游处理。

公开(公告)号：US20090296798A1

公开(公告)日：2009-12-03

申请号：US12295683

申请日：2007-04-05

申请人： Rami Banna ,  Mark A. Bickerstaff ,  Matthew E. Cooke ,  Adriel P. kind ,  Yi-Chen Li ,  Oliver Ridler ,  Uwe Sontowski ,  Charles N. A. Thomas ,  Long Ung ,  Koen Van den Beld ,  Benjamin J. Widdup ,  Graeme K. Woodward ,  Dominic Wing-Kin Yip ,  Gongyu Zhou

发明人： Rami Banna ,  Mark A. Bickerstaff ,  Matthew E. Cooke ,  Adriel P. kind ,  Yi-Chen Li ,  Oliver Ridler ,  Uwe Sontowski ,  Charles N. A. Thomas ,  Long Ung ,  Koen Van den Beld ,  Benjamin J. Widdup ,  Graeme K. Woodward ,  Dominic Wing-Kin Yip ,  Gongyu Zhou

IPC分类号： H03H7/40 ,  H04W4/00

CPC分类号： H04B1/70754 ,  H04B1/7097 ,  H04B2201/70701 ,  H04L25/03057 ,  H04L25/03292 ,  H04L2025/03617 ,  H04L2025/03687

摘要： In one embodiment, an HSDPA co-processor for 3GPP Release 6 Category 8 (7.2 Mb/s) HSDPA that provides all chip-rate, symbol-rate, physical-channel, and transport-channel processing for HSDPA in 90 nm CMOS. The co-processor design is scalable to all HSDPA data rates up to 14 Mb/s. The coprocessor implements an Advanced Receiver based on an NLMS equalizer, supports RX diversity and TX diversity, and provides up to 6.4 dB better performance than a typical single-antenna rake receiver. Thus, 3GPP R6 HSDPA functionality can be added to a legacy R99 modem using an HSDPA co-processor consistent with embodiments of the present invention, at a reasonable incremental cost and power.

摘要翻译： 在一个实施例中，用于3GPP版本6类别（7.2Mb / s）HSDPA的HSDPA协处理器为90nm CMOS中的HSDPA提供所有芯片速率，符号速率，物理信道和传输信道处理。 协处理器设计可扩展到高达14 Mb / s的所有HSDPA数据速率。 协处理器基于NLMS均衡器实现高级接收机，支持RX分集和TX分集，并且比典型的单天线耙式接收机提供高达6.4 dB的性能。 因此，3GPP R6 HSDPA功能可以以合理的增量成本和功率被添加到与本发明实施例一致的HSDPA协处理器的传统R99调制解调器。