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13 条记录 (耗时 0.067 秒)

    Hardware matrix computation for wireless receivers
    2.
    发明授权
    Hardware matrix computation for wireless receivers 有权
    无线接收机的硬件矩阵计算

    公开(公告)号：US07974997B2

    公开(公告)日：2011-07-05

    申请号：US11731174

    申请日：2007-03-30

    申请人： Eliahou Arviv ,  Robert L. Lang ,  Yi-Chen Li ,  Oliver Ridler ,  Xiao-an Wang

    发明人： Eliahou Arviv ,  Robert L. Lang ,  Yi-Chen Li ,  Oliver Ridler ,  Xiao-an Wang

    IPC分类号： G06F17/16

    CPC分类号： G06F17/16 ,  H04B1/707 ,  H04B2201/70707 ,  H04B2201/709727

    摘要： In one embodiment, a receiver including one or more signal-processing blocks and a hardware-based matrix co-processor. The one or more signal-processing blocks are adapted to generate a processed signal from a received signal. The hardware-based matrix co-processor includes two or more different matrix-computation engines, each adapted to perform a different matrix computation, and one or more shared hardware-computation units, each adapted to perform a mathematical operation. At least one signal-processing block is adapted to offload matrix-based signal processing to the hardware-based matrix co-processor. Each of the two or more different matrix-computation engines is adapted to offload the same type of mathematical processing to at least one of the one or more shared hardware-computation units.

    摘要翻译： 在一个实施例中，接收机包括一个或多个信号处理块和基于硬件的矩阵协处理器。 所述一个或多个信号处理块适于从接收到的信号产生经处理的信号。 基于硬件的矩阵协处理器包括两个或更多个不同的矩阵计算引擎，每个矩阵计算引擎适于执行不同的矩阵计算，以及一个或多个共享硬件计算单元，每个共享硬件计算单元适于执行数学运算。 至少一个信号处理块适于将基于矩阵的信号处理卸载到基于硬件的矩阵协处理器。 两个或更多个不同的矩阵计算引擎中的每一个适于将相同类型的数学处理卸载到一个或多个共享硬件计算单元中的至少一个。

    Hardware matrix computation for wireless receivers
    3.
    发明申请
    Hardware matrix computation for wireless receivers 有权
    无线接收机的硬件矩阵计算

    公开(公告)号：US20080243982A1

    公开(公告)日：2008-10-02

    申请号：US11731174

    申请日：2007-03-30

    申请人： Eliahou Arviv ,  Robert L. Lang ,  Yi-Chen Li ,  Oliver Ridler ,  Xiao-an Wang

    发明人： Eliahou Arviv ,  Robert L. Lang ,  Yi-Chen Li ,  Oliver Ridler ,  Xiao-an Wang

    IPC分类号： G06F17/10 ,  G06F7/32

    CPC分类号： G06F17/16 ,  H04B1/707 ,  H04B2201/70707 ,  H04B2201/709727

    摘要： In one embodiment, a receiver including one or more signal-processing blocks and a hardware-based matrix co-processor. The one or more signal-processing blocks are adapted to generate a processed signal from a received signal. The hardware-based matrix co-processor includes two or more different matrix-computation engines, each adapted to perform a different matrix computation, and one or more shared hardware-computation units, each adapted to perform a mathematical operation. At least one signal-processing block is adapted to offload matrix-based signal processing to the hardware-based matrix co-processor. Each of the two or more different matrix-computation engines is adapted to offload the same type of mathematical processing to at least one of the one or more shared hardware-computation units.

    摘要翻译： 在一个实施例中，接收机包括一个或多个信号处理块和基于硬件的矩阵协处理器。 所述一个或多个信号处理块适于从接收到的信号产生经处理的信号。 基于硬件的矩阵协处理器包括两个或更多个不同的矩阵计算引擎，每个矩阵计算引擎适于执行不同的矩阵计算，以及一个或多个共享硬件计算单元，每个共享硬件计算单元适于执行数学运算。 至少一个信号处理块适于将基于矩阵的信号处理卸载到基于硬件的矩阵协处理器。 两个或更多个不同的矩阵计算引擎中的每一个适于将相同类型的数学处理卸载到一个或多个共享硬件计算单元中的至少一个。

    Sound Processor Accessory
    6.
    发明申请
    Sound Processor Accessory 有权
    声音处理器配件

    公开(公告)号：US20140371815A1

    公开(公告)日：2014-12-18

    申请号：US13919226

    申请日：2013-06-17

    申请人： Oliver Ridler

    发明人： Oliver Ridler

    IPC分类号： A61N1/36

    CPC分类号： A61N1/36032 ,  A61N1/0541 ,  A61N1/36036 ,  H04R25/43 ,  H04R25/554 ,  H04R2225/021 ,  H04R2225/67

    摘要： Embodiments presented herein are generally directed to a sound processor accessory configured to be mechanically and electrically connected to a sound processor of an auditory prosthesis. The sound processor accessory comprises first and second sound input elements that are each configured to independently provide electrical signals representing sound signals to the sound processor via a shared connection.

    摘要翻译： 本文呈现的实施例通常涉及被配置为机械地和电连接到听觉假体的声音处理器的声音处理器附件。 声音处理器附件包括第一和第二声音输入元件，每个声音输入元件被配置为经由共享连接独立地向声音处理器提供表示声音信号的电信号。

    Communications circuit and method with reduced power consumption
    7.
    发明授权
    Communications circuit and method with reduced power consumption 有权
    具有降低功耗的通信电路和方法

    公开(公告)号：US08831603B2

    公开(公告)日：2014-09-09

    申请号：US11480296

    申请日：2006-06-30

    申请人： Christopher John Nicol ,  Oliver Ridler ,  Charles Nicholas Alexander Thomas

    发明人： Christopher John Nicol ,  Oliver Ridler ,  Charles Nicholas Alexander Thomas

    IPC分类号： H04B7/00 ,  H04B7/204 ,  H04W4/00 ,  H04W52/02 ,  H04W52/14

    CPC分类号： H04W52/0229 ,  H04W52/02 ,  H04W52/146 ,  Y02D70/1244

    摘要： A method of operating a communications circuit with at least one control channel and at least one data channel includes the steps of monitoring the at least one control channel, powering a receiver portion of the circuit when the at least one control channel indicates that data is to be received, and refraining from powering the receiver portion when the at least one control channel indicates that data is not to be received. The circuit can operate, for example, under the 3GPP HSDPA standard. Where desired, the clock and power supply to the receiver portion and a bit rate processing portion can be independently gated.

    摘要翻译： 一种使用至少一个控制信道和至少一个数据信道操作通信电路的方法包括以下步骤：当所述至少一个控制信道指示所述数据到达所述至少一个控制信道时监视所述至少一个控制信道，为所述电路的接收机部分供电; 并且当所述至少一个控制信道指示不接收到所述数据时，不接收对所述接收器部分供电。 该电路可以例如在3GPP HSDPA标准下操作。 如果需要，可以独立地选通到接收机部分和比特率处理部分的时钟和电源。

    Communications circuit and method with reduced power consumption
    8.
    发明申请
    Communications circuit and method with reduced power consumption 有权
    具有降低功耗的通信电路和方法

    公开(公告)号：US20080004008A1

    公开(公告)日：2008-01-03

    申请号：US11480296

    申请日：2006-06-30

    申请人： Christopher John Nicol ,  Oliver Ridler ,  Charles Nicholas Alexander Thomas

    发明人： Christopher John Nicol ,  Oliver Ridler ,  Charles Nicholas Alexander Thomas

    IPC分类号： H04Q7/20

    CPC分类号： H04W52/0229 ,  H04W52/02 ,  H04W52/146 ,  Y02D70/1244

    摘要： A method of operating a communications circuit with at least one control channel and at least one data channel includes the steps of monitoring the at least one control channel, powering a receiver portion of the circuit when the at least one control channel indicates that data is to be received, and refraining from powering the receiver portion when the at least one control channel indicates that data is not to be received. The circuit can operate, for example, under the 3GPP HSDPA standard. Where desired, the clock and power supply to the receiver portion and a bit rate processing portion can be independently gated.

    摘要翻译： 一种使用至少一个控制信道和至少一个数据信道操作通信电路的方法包括以下步骤：当所述至少一个控制信道指示所述数据到达所述至少一个控制信道时监视所述至少一个控制信道，为所述电路的接收机部分供电; 并且当所述至少一个控制信道指示不接收到所述数据时，不接收对所述接收器部分供电。 该电路可以例如在3GPP HSDPA标准下操作。 如果需要，可以独立地选通到接收机部分和比特率处理部分的时钟和电源。

    Selection of 1-out-of-n scrambled code blocks
    9.
    发明申请
    Selection of 1-out-of-n scrambled code blocks 审中-公开
    选择1-out-of-n加扰码块

    公开(公告)号：US20060239457A1

    公开(公告)日：2006-10-26

    申请号：US11114023

    申请日：2005-04-26

    申请人： Oliver Ridler ,  Benjamin Widdup ,  Graeme Woodward

    发明人： Oliver Ridler ,  Benjamin Widdup ,  Graeme Woodward

    IPC分类号： H04N7/167

    CPC分类号： H04L1/0059 ,  H03M13/3776 ,  H04L1/0045 ,  H04L1/0068 ,  H04L1/0072

    摘要： Apparatus and method to determine selection of a scrambled data channel before receipt of an entire data block. An initial portion of a block of data received in one of a plurality of scrambled data channels is decoded, then re-encoded. A value is computed related to the number of mis-matched data symbols based on a comparison of decoded/re-encoded data and the corresponding received data. A best one of the plurality of data channels is selected based on the computed value being beyond a given threshold value.

    摘要翻译： 在接收整个数据块之前确定加扰数据信道的选择的装置和方法。 在多个加扰数据信道之一中接收的数据块的初始部分被解码，然后被重新编码。 基于解码/再编码数据的比较和相应的接收数据，计算与错误匹配的数据符号的数量有关的值。 基于所计算的值超过给定阈值来选择多个数据通道中的最佳数据通道。