公开(公告)号：US20060110952A1

公开(公告)日：2006-05-25

申请号：US10995851

申请日：2004-11-22

申请人： Shekhar Borkar ,  Matthew Haycock ,  Stephen Mooney ,  Aaron Martin ,  Joseph Kennedy

发明人： Shekhar Borkar ,  Matthew Haycock ,  Stephen Mooney ,  Aaron Martin ,  Joseph Kennedy

IPC分类号： H05K1/00

CPC分类号： G06F13/4086

摘要： In some embodiments, the invention involves a system having a first group of integrated circuits connected in a truncated ring fashion, wherein the truncated ring includes a truncated region to allow for additional integrated circuits to be added to the ring. In some embodiments, the invention involves a system having a group of integrated circuits connected in a pseudo ring fashion, wherein the pseudo ring is created by data flow of bi-directional signaling between the integrated circuits. In some embodiments, the invention involves a system having a group of integrated circuits connected in a pseudo differential arrangement in which multiple conductors carrying signals share a common reference signal conductor.

摘要翻译： 在一些实施例中，本发明涉及具有以截头环方式连接的第一组集成电路的系统，其中所述截头环包括截取的区域，以允许将额外的集成电路添加到所述环中。 在一些实施例中，本发明涉及具有以伪环方式连接的一组集成电路的系统，其中通过集成电路之间的双向信令的数据流创建伪环。 在一些实施例中，本发明涉及一种具有以伪差分布置连接的一组集成电路的系统，其中携带多个导体的信号共用公共参考信号导体。

公开(公告)号：US20120221884A1

公开(公告)日：2012-08-30

申请号：US13036826

申请日：2011-02-28

申请人： Nicholas P. Carter ,  Donald S. Gardner ,  Eric C. Hannah ,  Helia Naeimi ,  Shekhar Y. Borkar ,  Matthew Haycock

发明人： Nicholas P. Carter ,  Donald S. Gardner ,  Eric C. Hannah ,  Helia Naeimi ,  Shekhar Y. Borkar ,  Matthew Haycock

IPC分类号： G06F11/07

CPC分类号： G06F11/0781 ,  G06F11/0772 ,  G06F11/0793 ,  G06F11/1425 ,  G06F11/1428

摘要： Generally, this disclosure provides error management across hardware and software layers to enable hardware and software to deliver reliable operation in the face of errors and hardware variation due to aging, manufacturing tolerances, etc. In one embodiment, an error management module is provided that gathers information from the hardware and software layers, and detects and diagnoses errors. A hardware or software recovery technique may be selected to provide efficient operation, and, in some embodiments, the hardware device may be reconfigured to prevent future errors and to permit the hardware device to operate despite a permanent error.

摘要翻译： 通常，本公开提供跨越硬件和软件层的错误管理，以使硬件和软件能够在由于老化，制造公差等导致的错误和硬件变化的情况下提供可靠的操作。在一个实施例中，提供了一种错误管理模块， 来自硬件和软件层的信息，并检测和诊断错误。 可以选择硬件或软件恢复技术来提供有效的操作，并且在一些实施例中，硬件设备可以被重新配置以防止将来的错误，并允许硬件设备在永久性错误的情况下操作。

公开(公告)号：US20070153445A1

公开(公告)日：2007-07-05

申请号：US11323370

申请日：2005-12-29

申请人： Frank O'Mahony ,  Bryan Casper ,  James Jaussi ,  Matthew Haycock ,  Joseph Kennedy ,  Mozhgan Mansuri ,  Stephen Mooney

发明人： Frank O'Mahony ,  Bryan Casper ,  James Jaussi ,  Matthew Haycock ,  Joseph Kennedy ,  Mozhgan Mansuri ,  Stephen Mooney

IPC分类号： H02B1/00

CPC分类号： H04L25/0278 ,  H03K5/15013 ,  H04L25/0292 ,  H04L25/0298

摘要： For one disclosed embodiment, an integrated circuit may comprise an internal transmission line in one or more layers of the integrated circuit. The internal transmission line may be coupled to receive a signal from an external transmission line at a first end of the internal transmission line without use of termination circuitry. The internal transmission line may transmit the signal passively to a second end of the internal transmission line. The integrated circuit may also comprise first circuitry having an input coupled to the internal transmission line at a first location of the internal transmission line to receive the signal and second circuitry having an input coupled to the internal transmission line at a second location of the internal transmission line to receive the signal. The second location may be different from the first location. Other embodiments are also disclosed.

摘要翻译： 对于一个公开的实施例，集成电路可以包括集成电路的一个或多个层中的内部传输线。 内部传输线可以被耦合以在内部传输线的第一端处接收来自外部传输线的信号，而不使用终端电路。 内部传输线路可以将信号被动地发送到内部传输线路的第二端。 集成电路还可以包括第一电路，其具有在内部传输线的第一位置处耦合到内部传输线的输入以接收信号，并且第二电路具有在内部传输的第二位置处耦合到内部传输线的输入 线接收信号。 第二位置可以不同于第一位置。 还公开了其他实施例。

公开(公告)号：US20050248367A1

公开(公告)日：2005-11-10

申请号：US11141262

申请日：2005-05-31

申请人： Matthew Haycock ,  Amaresh Pangal

发明人： Matthew Haycock ,  Amaresh Pangal

IPC分类号： G06F1/04 ,  G06F1/12 ,  H03K19/00

CPC分类号： G06F1/12

摘要： A digital bus includes a transmitter unit, a receiver unit, and a transmission medium to couple the transmitter unit to the receiver unit and to provide a path for exchanging information between the transmitter unit and the receiver unit. The receiver unit includes a first-in-first-out (FIFO) unit and a synchronizer unit for receiving information from the transmitter unit. The synchronizer unit receives a plurality of write clock signals and a reset signal and generates a read reset signal positioned with respect to the plurality write clock signals and a sample clock signal. The read reset signal has a latency with respect to each of the plurality of write reset signals of between 0 and 1 clock cycles.

摘要翻译： 数字总线包括发射机单元，接收机单元和用于将发射机单元耦合到接收机单元并且提供用于在发射机单元和接收机单元之间交换信息的路径的传输介质。 接收机单元包括先进先出（FIFO）单元和用于从发射机单元接收信息的同步器单元。 同步器单元接收多个写时钟信号和复位信号，并产生相对于多个写入时钟信号定位的读取复位信号和采样时钟信号。 读取复位信号相对于多个写入复位信号中的每一个在0和1个时钟周期之间具有等待时间。