公开(公告)号：US5862354A

公开(公告)日：1999-01-19

申请号：US611035

申请日：1996-03-05

申请人： Andreas Curiger ,  Wendell L. Little ,  Matthew K. Adams

发明人： Andreas Curiger ,  Wendell L. Little ,  Matthew K. Adams

IPC分类号： G06F3/02 ,  G06F13/38 ,  G06F13/00

CPC分类号： G06F13/385

摘要： A processor system is disclosed wherein said processor system is adapted to communicate over at least one one-wire network utilizing one-wire communications protocol. For the embodiment of the invention in which the processor system acts as a network master, the processor system includes a master UART especially configured to control communications over such network according to one-wire protocol. For the embodiment of the invention in which the processor communicates over two one-wire networks, the processor system includes a first UART which acts as a slave and a second UART which acts as a master.

摘要翻译： 公开了一种处理器系统，其中所述处理器系统适于通过使用单线通信协议的至少一个单线网络进行通信。 对于其中处理器系统充当网络主机的本发明的实施例，处理器系统包括主UART，其特别地被配置为根据单线协议来控制通过这样的网络的通信。 对于其中处理器通过两个一线网络通信的本发明的实施例，处理器系统包括用作从设备的第一UART和作为主设备的第二UART。

公开(公告)号：US5758060A

公开(公告)日：1998-05-26

申请号：US611037

申请日：1996-03-05

申请人： Wendell L. Little ,  Matthew K. Adams ,  David A. Bunsey, Jr.

发明人： Wendell L. Little ,  Matthew K. Adams ,  David A. Bunsey, Jr.

IPC分类号： G06F11/28 ,  G06F11/00

CPC分类号： G06F11/28

摘要： A hardware circuit for verifying the execution of software is disclosed wherein the circuit compares a stored value with another value that is stored at at least one predetermined time in the course of program execution. If the two values correspond in some predetermined fashion then it is verified with a level of certainty that the program executed the program steps at or near the predetermined times.

摘要翻译： 公开了一种用于验证软件执行的硬件电路，其中电路将存储的值与在程序执行过程中至少一个预定时间存储的另一个值进行比较。 如果这两个值以某种预定的方式对应，则以确定性程度验证程序在预定时间或接近预定时间执行程序步骤。

公开(公告)号：US5097154A

公开(公告)日：1992-03-17

申请号：US567437

申请日：1990-08-13

申请人： Matthew K. Adams

发明人： Matthew K. Adams

IPC分类号： G06F1/30 ,  G06F11/00 ,  G06F11/10 ,  G06F11/14 ,  G06F11/16

CPC分类号： G06F1/30 ,  G06F11/1415 ,  G06F11/16 ,  G06F11/1604 ,  G06F11/0754 ,  G06F11/0757 ,  G06F11/10 ,  G06F11/1438 ,  G06F11/1441 ,  G06F11/2015

摘要： An adjunct chip, usable as a peripheral to a microprocessor, which detects power failure, and which puts the microprocessor into a known state upon power down. In order to reliably and stably put the microprocessor into a known state, several clocks are generated after the reset signal. However, since the power supply is falling, it is possible that the crystal-controlled oscillator may already have become unreliable. Therefore, a simple logic circuit (a ring oscillator, in the presently preferred embodiment) is used to generate the needed additional clocks at power-down. The switch from crystal-controlled oscillator to ring oscillator is stabilized by using a latched multiplexer to switch between the two oscillator inputs. The latch adds hysteresis to the switching characteristic, avoiding any problems of switching jitter.

摘要翻译： 辅助芯片，可用作微处理器的外围设备，其检测电力故障，并且在掉电时将微处理器置于已知状态。 为了可靠且稳定地将微处理器置于已知状态，在复位信号之后产生几个时钟。 然而，由于电源下降，晶体振荡器可能已经变得不可靠了。 因此，简单的逻辑电路（在当前优选实施例中是环形振荡器）用于在掉电时产生所需的附加时钟。 通过使用锁存的多路复用器在两个振荡器输入之间切换，从晶体振荡器到环形振荡器的切换是稳定的。 锁存器对开关特性增加了滞后，避免了开关抖动的任何问题。

公开(公告)号：US5381540A

公开(公告)日：1995-01-10

申请号：US985513

申请日：1992-12-02

申请人： Matthew K. Adams ,  Wendell L. Little ,  Stephen N. Grider

发明人： Matthew K. Adams ,  Wendell L. Little ,  Stephen N. Grider

IPC分类号： G06F13/26 ,  G06F13/14

CPC分类号： G06F13/26

摘要： Interrupt circuitry for a processor comprises a plurality of interrupt inputs, an interrupt output, combinatorial logic with a plurality of combinatorial logic inputs connected to the plurality of interrupt inputs and with a combinatorial logic output connected to the interrupt output wherein an interrupt output signal at the interrupt output is a function of interrupt signals at the plurality of interrupt inputs; and an interrupt mode select connected to the combinatorial logic wherein an interrupt mode select signal from the interrupt mode select controls the function. The interrupt mode select signal from the interrupt mode select selects the function to be either AND or OR. The circuitry also comprises a mask register having a plurality of mask register inputs and a plurality of mask register outputs, the plurality of mask register inputs connected to the plurality of interrupt inputs and the plurality of mask register outputs connected to the plurality of combinatorial logic inputs wherein a mask register bit pattern in the mask register conditions a corresponding subset (possibly empty) of the interrupt signals at the plurality of interrupt inputs to make the function and the interrupt output signal at the interrupt output not depend upon the corresponding subset.

摘要翻译： 用于处理器的中断电路包括多个中断输入，中断输出，组合逻辑，多个组合逻辑输入连接到多个中断输入，以及连接到中断输出的组合逻辑输出，其中中断输出信号 中断输出是多个中断输入端的中断信号的函数; 以及连接到组合逻辑的中断模式选择，其中来自中断模式选择的中断模式选择信号控制该功能。 来自中断模式的中断模式选择信号选择将该功能选择为或或。 电路还包括具有多个屏蔽寄存器输入和多个屏蔽寄存器输出的屏蔽寄存器，多个屏蔽寄存器输入连接到多个中断输入以及连接到多个组合逻辑输入的多个屏蔽寄存器输出 其中掩模寄存器中的掩码寄存器位模式对多个中断输入端的中断信号的对应子集（可能是空的）进​​行调整，以使中断输出处的功能和中断输出信号不依赖于对应的子集。

公开(公告)号：US5099153A

公开(公告)日：1992-03-24

申请号：US567397

申请日：1990-08-13

申请人： Matthew K. Adams

发明人： Matthew K. Adams

IPC分类号： G06F1/04 ,  G06F11/30

CPC分类号： G06F1/04

摘要： A clock monitor circuit which is frequency-independent. The crystal terminals on a circuit being monitored for activity may be considered as an inverter combined with a phase delay. The innovative circuit has clock-output and clock-input terminals which are connected to the clock terminals on the circuit being monitored. When a rising edge appears on the clock-output terminal, the clock-input line is sampled: if the circuit being monitored is properly active, the level on the clock-input line will be high. Similarly, when a falling edge appears on the clock-output terminal, the clock-input line is sampled: if the circuit being monitored is properly active, the level on the clock-input line will be low. Whenever a low level is detected on a rising edge, or a high level on a falling edge, a counter chain will start counting down. The counter chain will be reset only when a high level is detected on a rising edge AND a low level is detected on the next falling edge. Thus, when the circuit being monitored becomes inactive, the counter chain will start to count down, and will eventually reach zero and generate a watchdog interrupt or reset.

摘要翻译： 时钟监视电路，与频率无关。 被监控的电路上的晶体端子可以被认为是与相位延迟相结合的逆变器。 创新的电路具有时钟输出和时钟输入端子，连接到被监控电路上的时钟端子。 当时钟输出端子出现上升沿时，时钟输入线被采样：如果正在监视的电路正常工作，时钟输入线上的电平将变高。 类似地，当时钟输出端子出现下降沿时，时钟输入线路被采样：如果被监视的电路正常工作，则时钟输入线路上的电平将为低电平。 无论何时在上升沿检测到低电平，或在下降沿检测到高电平，反向链将开始倒计时。 仅当在上升沿检测到高电平时，才会复位反向链，并在下一个下降沿检测到低电平。 因此，当被监视的电路变为不活动时，反向链将开始倒计时，最终将达到零，并产生看门狗中断或复位。