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1.发明授权Universal asynchronous receiver/transmitter (UART) slave device containing an identifier for communication on a one-wire bus 失效通用异步接收/发送器（UART）从器件包含用于在单线总线上进行通信的标识符
公开(公告)号：US5862354A
公开(公告)日：1999-01-19
申请号：US611035
申请日：1996-03-05
CPC分类号： G06F13/385
摘要： A processor system is disclosed wherein said processor system is adapted to communicate over at least one one-wire network utilizing one-wire communications protocol. For the embodiment of the invention in which the processor system acts as a network master, the processor system includes a master UART especially configured to control communications over such network according to one-wire protocol. For the embodiment of the invention in which the processor communicates over two one-wire networks, the processor system includes a first UART which acts as a slave and a second UART which acts as a master.
摘要翻译： 公开了一种处理器系统，其中所述处理器系统适于通过使用单线通信协议的至少一个单线网络进行通信。 对于其中处理器系统充当网络主机的本发明的实施例，处理器系统包括主UART，其特别地被配置为根据单线协议来控制通过这样的网络的通信。 对于其中处理器通过两个一线网络通信的本发明的实施例，处理器系统包括用作从设备的第一UART和作为主设备的第二UART。
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2.发明授权Integrated circuit having hardware circuitry to prevent electrical or thermal stressing of the silicon circuitry 有权具有用于防止硅电路的电应力或热应力的硬件电路的集成电路公开(公告)号：US06330668B1
公开(公告)日：2001-12-11
申请号：US09133946
申请日：1998-08-14
申请人： Andreas Curiger , Wendell L. Little
发明人： Andreas Curiger , Wendell L. Little
IPC分类号： G06F1130
CPC分类号： G06F21/75 , G05B19/0428 , G05B2219/24205 , G06F11/004 , G06F11/24 , G06F11/3013 , G06F11/3024 , G06F11/3058 , G06F21/71 , G06F21/72 , G06F2221/2101 , G06F2221/2143 , G06K19/073 , G06K19/07363
摘要： An integrated circuit, such as a microprocessor, which incorporates hardware mechanisms to prevent the circuitry from operating outside the proper bounds of design. The hardware circuitry prevents the microprocessor circuitry from being forced to operate at clock speeds that are greater than it is designed for, from operating at temperatures above or below that which it is designed for, and from being forced to operate at voltages that are above or below voltages that the microprocessor is designed to operate at.
摘要翻译： 诸如微处理器的集成电路，其集成了硬件机制以防止电路在设计的正确界限之外运行。 硬件电路防止微处理器电路被强制以比在其设计的温度高于或低于其设计的温度下工作的时钟速度操作，并且被强制在高于或高于 低于微处理器设计工作的电压。
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3.发明授权Hardware for verifying that software has not skipped a predetermined amount of code 失效用于验证该软件未跳过预定量代码的硬件
公开(公告)号：US5758060A
公开(公告)日：1998-05-26
申请号：US611037
申请日：1996-03-05
CPC分类号： G06F11/28
摘要： A hardware circuit for verifying the execution of software is disclosed wherein the circuit compares a stored value with another value that is stored at at least one predetermined time in the course of program execution. If the two values correspond in some predetermined fashion then it is verified with a level of certainty that the program executed the program steps at or near the predetermined times.
摘要翻译： 公开了一种用于验证软件执行的硬件电路，其中电路将存储的值与在程序执行过程中至少一个预定时间存储的另一个值进行比较。 如果这两个值以某种预定的方式对应，则以确定性程度验证程序在预定时间或接近预定时间执行程序步骤。
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公开(公告)号：US5381540A
公开(公告)日：1995-01-10
申请号：US985513
申请日：1992-12-02
CPC分类号： G06F13/26
摘要： Interrupt circuitry for a processor comprises a plurality of interrupt inputs, an interrupt output, combinatorial logic with a plurality of combinatorial logic inputs connected to the plurality of interrupt inputs and with a combinatorial logic output connected to the interrupt output wherein an interrupt output signal at the interrupt output is a function of interrupt signals at the plurality of interrupt inputs; and an interrupt mode select connected to the combinatorial logic wherein an interrupt mode select signal from the interrupt mode select controls the function. The interrupt mode select signal from the interrupt mode select selects the function to be either AND or OR. The circuitry also comprises a mask register having a plurality of mask register inputs and a plurality of mask register outputs, the plurality of mask register inputs connected to the plurality of interrupt inputs and the plurality of mask register outputs connected to the plurality of combinatorial logic inputs wherein a mask register bit pattern in the mask register conditions a corresponding subset (possibly empty) of the interrupt signals at the plurality of interrupt inputs to make the function and the interrupt output signal at the interrupt output not depend upon the corresponding subset.
摘要翻译： 用于处理器的中断电路包括多个中断输入，中断输出，组合逻辑，多个组合逻辑输入连接到多个中断输入，以及连接到中断输出的组合逻辑输出，其中中断输出信号 中断输出是多个中断输入端的中断信号的函数; 以及连接到组合逻辑的中断模式选择，其中来自中断模式选择的中断模式选择信号控制该功能。 来自中断模式的中断模式选择信号选择将该功能选择为或或。 电路还包括具有多个屏蔽寄存器输入和多个屏蔽寄存器输出的屏蔽寄存器，多个屏蔽寄存器输入连接到多个中断输入以及连接到多个组合逻辑输入的多个屏蔽寄存器输出 其中掩模寄存器中的掩码寄存器位模式对多个中断输入端的中断信号的对应子集（可能是空的）进行调整，以使中断输出处的功能和中断输出信号不依赖于对应的子集。
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5.发明授权
公开(公告)号：US5998858A
公开(公告)日：1999-12-07
申请号：US684644
申请日：1996-07-19
申请人： Wendell L. Little , Stephen M. Curry , Steven N. Grider , Mark L. Thrower , Steven N. Hass , Michael L. Bolan , Ricky D. Fieseler , Bradley M. Harrington
发明人： Wendell L. Little , Stephen M. Curry , Steven N. Grider , Mark L. Thrower , Steven N. Hass , Michael L. Bolan , Ricky D. Fieseler , Bradley M. Harrington
IPC分类号： G06F1/00 , G06F7/58 , G06F7/72 , G06F21/00 , G07F7/10 , G11C5/00 , G11C5/14 , G11C7/24 , G11C8/20 , H01L23/58 , H04L9/08 , H04L9/30 , H04L25/02 , H01L23/02
CPC分类号： G06F7/588 , G06F11/1004 , G06F21/602 , G06F21/72 , G06F21/73 , G06F21/75 , G06F21/81 , G06F21/86 , G06F21/87 , G06F9/30134 , G06Q20/341 , G06Q20/40975 , G07F7/082 , G07F7/1008 , G11C5/06 , G11C5/143 , G11C7/24 , G11C8/20 , H01L23/57 , H04L25/026 , G06F2211/007 , G06F2221/2143 , G06F2221/2153 , H01L2224/16225 , H01L2924/16152 , H01L2924/3011 , Y10S257/922
摘要： A secure electronic data module containing a monolithic semiconductor chip of the type having a memory that is protected by a combination of hardware and software mechanisms such that unauthorized access to the data stored in the memory is prevented. The monolithic semiconductor chip comprises a plurality of solder bumps for attaching the chip to a substrate that may be a printed circuit board or another chip; a multi-level interlaced power and ground lines using minimum geometries; and a detection circuit block for detecting an external trip signal that may be produced by a pre-specified change in an operating condition brought on by unauthorized accessing, or an internal trip signal that may be produced by shorting of power and ground lines or by a change in an oscillator's frequency, also associated with or appurtenant to unauthorized accessing of the secure memory.
摘要翻译： 一种安全的电子数据模块，其包含具有由硬件和软件机构的组合保护的存储器的类型的单片半导体芯片，从而防止对存储在存储器中的数据的未经授权的访问。 单片半导体芯片包括用于将芯片附接到可以是印刷电路板或另一芯片的基板的多个焊料凸块; 使用最小几何形状的多级隔行电源和地线; 以及检测电路块，用于检测可以通过未经授权的访问引起的操作条件的预先指定的变化产生的外部跳闸信号，或者可以通过短路电源和地线或由 改变振荡器的频率，也与安全存储器的未授权访问相关联或附加。
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公开(公告)号：US5850450A
公开(公告)日：1998-12-15
申请号：US690272
申请日：1996-07-19
申请人： Peter Schweitzer , Stephen M. Curry , Wendell L. Little , Bryan M. Armstrong , Christopher W. Fox , Donald W. Loomis
发明人： Peter Schweitzer , Stephen M. Curry , Wendell L. Little , Bryan M. Armstrong , Christopher W. Fox , Donald W. Loomis
IPC分类号： G06F1/00 , G06F7/58 , G06F7/72 , G06F21/00 , G07F7/10 , G11C5/00 , G11C5/14 , G11C7/24 , G11C8/20 , H01L23/58 , H04L9/08 , H04L9/30 , H04L25/02 , H04L9/00
CPC分类号： G06F7/588 , G06F11/1004 , G06F21/602 , G06F21/72 , G06F21/73 , G06F21/75 , G06F21/81 , G06F21/86 , G06F21/87 , G06F9/30134 , G06Q20/341 , G06Q20/40975 , G07F7/082 , G07F7/1008 , G11C5/06 , G11C5/143 , G11C7/24 , G11C8/20 , H01L23/57 , H04L25/026 , G06F2211/007 , G06F2221/2143 , G06F2221/2153 , H01L2224/16225 , H01L2924/16152 , H01L2924/3011 , Y10S257/922
摘要： A portable electronic data module for secure transactions, the electronic data module having a random number generator and an optimized co-processor for producing unbreakable key sets for a two-key cryptosystem. A real-time clock is sampled depending upon an external random event series such as power-ups of the data module by a host apparatus, and based upon the contents of the sample thus obtained, the entropy of a previously-loaded accumulator is further enhanced to achieve a pool of true random numbers. By repeatedly requesting random bytes of information from said pool of random numbers, large random numbers are created which are then rendered prime and used for key set creation.
摘要翻译： 一种用于安全交易的便携式电子数据模块，所述电子数据模块具有随机数发生器和优化的协处理器，用于为双密码密码系统产生不可破坏的密钥集。 实时时钟取决于外部随机事件序列，例如主机设备对数据模块的上电，并且基于如此获得的样本的内容，进一步增强预先加载的累加器的熵 实现真正的随机数字池。 通过从所述随机数字池重复地请求随机字节的信息，创建大的随机数，然后将其渲染为素数并用于创建密钥集。
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公开(公告)号：US5812004A
公开(公告)日：1998-09-22
申请号：US736002
申请日：1996-10-23
申请人： Wendell L. Little
发明人： Wendell L. Little
CPC分类号： G06F1/324 , G06F1/08 , G06F1/32 , Y02B60/1217
摘要： A circuit, for incorporation into an electrical system, for providing a clock signal frequency to other circuitry such as a microprocessor and/or co-processor circuitry. The clock signal frequency varies its speed depending on the available voltage and current from a host power source. The circuit maximizes clock frequency by lowering the available voltage and increasing the available supply current. The circuit can therefore provide a higher clock speed and more current for switching transistors.
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公开(公告)号：US4857767A
公开(公告)日：1989-08-15
申请号：US106537
申请日：1988-03-03
IPC分类号： H03K19/017 , H03K19/177
CPC分类号： H03K19/01742 , H03K19/1772
摘要： A high density pull-up circuit provides a sustaining pull-up voltage for a logic node such as, for example, a precharged column in a programmable logic array (PLA). The pull-up circuit employs a current source and a first current mirror circuit which in turn drives a plurality of second mirror transistors, each of the second mirror transistors being coupled between a positive supply voltage and one of the column lines of the PLA.
摘要翻译： 高密度上拉电路为逻辑节点（例如可编程逻辑阵列（PLA）中的预充电列）提供维持上拉电压。 上拉电路采用电流源和第一电流镜电路，该电路又驱动多个第二反射镜晶体管，每个第二镜晶体管耦合在正电源电压和PLA的一列列线之间。
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9.发明授权
公开(公告)号：US06038655A
公开(公告)日：2000-03-14
申请号：US783718
申请日：1997-01-16
IPC分类号： G06F1/08 , H03K19/003 , G06F9/35
CPC分类号： G06F1/08 , H03K19/00361
摘要： A microprocessor on-board RAM provides both the usual random access by addressing and a subset of memory cells with their contents continually available on a secondary bus paralleling the data bus. This secondary bus may be used for register indirect addressing without a separate register read when the RAM subset includes the registers for register indirect addressing. The processor also has a two stage output driver for limiting maximum output current and feedback-controlled clock period partitioning.
摘要翻译： 微处理器板载RAM通过寻址和一个存储器单元的子集提供通常的随机存取，其内容在与数据总线并行的辅助总线上连续可用。 当RAM子集包含用于寄存器间接寻址的寄存器时，该辅助总线可用于寄存器间接寻址，而不需要单独的寄存器读取。 处理器还具有两级输出驱动器，用于限制最大输出电流和反馈控制的时钟周期分区。
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10.发明授权
公开(公告)号：US5903767A
公开(公告)日：1999-05-11
申请号：US834880
申请日：1997-04-07
申请人： Wendell L. Little
发明人： Wendell L. Little
CPC分类号： G06F11/0754 , G06F1/24 , G06F1/30 , G06F1/3203 , G06F1/3209 , G06F11/1415
摘要： A system which includes a microprocessor (or microcontroller) and an auxiliary chip which monitors the system power supply voltage and performs related functions for the microprocessor. Another of the innovative teachings set forth in the present application is that the microprocessor can access the auxiliary chip to ascertain the power history. That is, the microprocessor can direct an interrupt to the auxiliary chip, which will cause the auxiliary chip to respond with a signal which indicates to the microprocessor whether the power supply voltage is heading up or down. When the microprocessor is reset at power-up, and detects that the power supply voltage is still marginal, the present invention permits the microprocessor to determine (by querying the auxiliary chip) whether the supply voltage is marginal so that the microprocessor does not go into full operation until the supply voltage is high enough.
摘要翻译： 一种包括微处理器（或微控制器）和辅助芯片的系统，其监视系统电源电压并执行微处理器的相关功能。 本申请中提出的另一个创新教导是微处理器可以访问辅助芯片以确定功率历史。 也就是说，微处理器可以将辅助芯片引导中断，这将导致辅助芯片以向微处理器指示电源电压是向上还是向下的信号进行响应。 当微处理器在上电复位并且检测到电源电压仍然是边缘时，本发明允许微处理器确定（通过查询辅助芯片）电源电压是否是边缘的，使得微处理器不进入 全面运行，直到电源电压足够高。
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