公开(公告)号：US06734711B1

公开(公告)日：2004-05-11

申请号：US10404267

申请日：2003-04-01

申请人： Eugene B. Hinterscher

发明人： Eugene B. Hinterscher

IPC分类号： H03K508

CPC分类号： H03K5/08 ,  H03K5/1252 ,  H04L25/0292

摘要： An input transition stabilizer circuit, adapted to stabilize an input transition of a signal appearing at the input of an input circuit, the input transition stabilizer circuit includes a resistor having a first terminal connected to the input of the input circuit;, and a capacitor. A first MOS device is connected by a source and a drain between a second terminal of the resistor and a first terminal of the capacitor, while a second MOS device is connected by a source and a drain between a second terminal of the capacitor and ground. A delay circuit is adapted to provide a signal to a gate of the first MOS device and a gate of the second MOS device corresponding to a signal at the input of the input circuit, but delayed by a first predetermined interval. In some embodiments the delay circuit is provided in two parts, with the signal provided to the first MOS device being delayed by a further amount, as compared with the signal provided to the second MOS device.

摘要翻译： 输入转变稳定器电路，其适于稳定出现在输入电路的输入端的信号的输入转变，所述输入转变稳定器电路包括具有连接到所述输入电路的输入的第一端子的电阻器和电容器。 第一MOS器件通过电阻器的第二端子和电容器的第一端子之间的源极和漏极连接，而第二MOS器件通过电容器的第二端子与接地之间的源极和漏极连接。 延迟电路适于向第一MOS器件的栅极和第二MOS器件的栅极提供信号，该栅极与输入电路的输入处的信号相对应，但延迟第一预定间隔。 在一些实施例中，与提供给第二MOS器件的信号相比，延迟电路分两部分提供，提供给第一MOS器件的信号被延迟另外的量。

公开(公告)号：US06661255B2

公开(公告)日：2003-12-09

申请号：US10179042

申请日：2002-06-25

申请人： Hiroshi Watanabe

发明人： Hiroshi Watanabe

IPC分类号： H03K508

CPC分类号： H03K17/002 ,  H03K17/223

摘要： An interface circuit for a printer to prevent transmission of an incorrect control signal when power is input into the printer. The interface circuit improves the stability of the printer at the initial state of the rise of power supply voltages, and prevents erroneous operation. After power is input, in a switching control part 110, a flip-flop X23 is reset, a level change of output signals s1-s5 of an input part 100 is detected by a NAND gate X21, and an output signal s9 of the flip-flop X23 is raised. In a switching part 120, when the signal s9 is at low level, output signals s10-s14 are held at high level, and when the signal s9 is at high level, the output signals s1-s5 of the input part 100 are output to an output part 130. Thus, the output signals are held after the power input, and after the input signal rises, the signal transfer function is started, so that the output of incorrect control signals can be prevented, and thereby erroneous operation of a printer can be prevented.

摘要翻译： 一种用于打印机的接口电路，用于当电力输入打印机时防止发送不正确的控制信号。 接口电路在电源电压上升的初始状态下提高了打印机的稳定性，并防止了错误的操作。 在电源被输入之后，在切换控制部分110中，触发器X23被复位，由与非门X21检测输入部分100的输出信号s1-s5的电平变化，并且翻转的输出信号s9 -flop X23升高。 在切换部分120中，当信号s9处于低电平时，输出信号s10-s14保持在高电平，并且当信号s9处于高电平时，输入部分100的输出信号s1-s5输出到 输出部分130.因此，输出信号在电源输入之后保持，并且在输入信号上升之后，信号传递功能开始，从而可以防止错误控制信号的输出，从而打印机的错误操作 可以防止。

公开(公告)号：US06614282B2

公开(公告)日：2003-09-02

申请号：US10270808

申请日：2002-10-14

申请人： Hirofumi Abe ,  Hiroshi Fujii ,  Sinichi Noda ,  Hideaki Ishihara

发明人： Hirofumi Abe ,  Hiroshi Fujii ,  Sinichi Noda ,  Hideaki Ishihara

IPC分类号： H03K508

CPC分类号： H03M1/1295

摘要： A comparator, having an offset of 0.1V, compares a terminal voltage Vin1 with a clamp voltage VCL (5.1V). When an overvoltage input exceeding the VCL is entered to an input terminal, the comparator turns on a transistor Q11. The current flows across an externally provided resistor R11, the input terminal, and the transistor Q11, and flows into an output terminal of an operational amplifier. With a voltage drop at the resistor R11, the terminal voltage Vin1 starts decreasing toward an output voltage Vc of the operational amplifier.

摘要翻译： 具有0.1V偏移的比较器将终端电压Vin1与钳位电压VCL（5.1V）进行比较。 当超过VCL的过压输入被输入到输入端时，比较器接通晶体管Q11。 电流流过外部提供的电阻器R11，输入端子和晶体管Q11，并流入运算放大器的输出端。 在电阻器R11处具有电压降，端子电压Vin1开始朝向运算放大器的输出电压Vc降低。

公开(公告)号：US06590435B1

公开(公告)日：2003-07-08

申请号：US09931789

申请日：2001-08-16

申请人： Douglas M. Hannan ,  David J. Haas

发明人： Douglas M. Hannan ,  David J. Haas

IPC分类号： H03K508

CPC分类号： H03F3/45179 ,  H03F2203/45394 ,  H03F2203/45636 ,  H03F2203/45702 ,  H03K5/08

摘要： A method and apparatus that restrict the differential output voltage (VOD) for an LVDS input buffer is provided. Specifically, VOD is prevented from exceeding a predetermined threshold. The input and output common-mode voltage, as well as the input and output differential voltage swing, are maintained during the VOD restriction. The VOD restriction reduces output jitter of the LVDS input buffer and provides a more robust LVDS system as compared to an LVDS system not using a VOD restriction circuit. Clamping circuits are used to restrict the VOD. Each half of the differential output voltage may be clamped to restrict the differential output voltage. The clamping circuits are activated in response to the VOD reaching the predetermined threshold. When a clamping circuit is active, an alternate current path is provided maintaining the level of the signal before clamping.

摘要翻译： 提供限制LVDS输入缓冲器的差分输出电压（VOD）的方法和装置。 具体地，防止VOD超过预定阈值。 在VOD限制期间，保持输入和输出共模电压以及输入和输出差分电压摆幅。 与不使用VOD限制电路的LVDS系统相比，VOD限制降低了LVDS输入缓冲器的输出抖动，并提供了更强大的LVDS系统。 钳位电路用于限制VOD。 差分输出电压的每一半可以被钳位以限制差分输出电压。 钳位电路响应于VOD达到预定阈值而被激活。 当钳位电路有效时，提供交替电流通路，保持钳位前的信号电平。

公开(公告)号：US06504418B1

公开(公告)日：2003-01-07

申请号：US09660423

申请日：2000-09-12

申请人： Terry C. Coughlin, Jr.

发明人： Terry C. Coughlin, Jr.

IPC分类号： H03K508

CPC分类号： H03K19/00315

摘要： A high voltage tolerant CMOS input/output interface circuit. In this circuit, a process feature called “dual-gate” or “thick-oxide” process is used on any devices that will be exposed to high voltage. The thick-oxide devices have a larger capacitance and lower bandwidth, and therefore, preferably, they are only used where exposure to high voltage can cause damage. The remaining devices on the interface circuit may all use a standard process with the thinner oxide, allowing the I/O and the core IC to run at maximum speed. The circuit design topology also limits the number of devices that are exposed to high voltage. Preferably, the protection scheme is broken down into two parts: the driver and receiver.

摘要翻译： 高耐压CMOS输入/输出接口电路。 在该电路中，在将被暴露于高电压的任何器件上使用称为“双栅极”或“厚氧化物”工艺的工艺特征。 厚氧化物器件具有较大的电容和较低的带宽，因此，优选地，它们仅在暴露于高电压可能导致损坏的情况下使用。 接口电路上的其余器件都可以使用较薄氧化物的标准工艺，允许I / O和核心IC以最大速度运行。 电路设计拓扑也限制了暴露于高电压的器件数量。 优选地，保护方案分为两部分：驱动器和接收器。

公开(公告)号：US06483365B2

公开(公告)日：2002-11-19

申请号：US10100846

申请日：2002-03-19

申请人： Yasuyuki Morishita

发明人： Yasuyuki Morishita

IPC分类号： H03K508

CPC分类号： H01L27/0266 ,  H03F1/523

摘要： A semiconductor device is provided with a signal terminal, a high potential side power supply terminal, a low potential side power supply terminal, a first wiring connected to the high potential side power supply terminal, a second wiring connected to the low potential side power supply terminal, and an internal circuit to which power is supplied from the first and second wirings. Further the semiconductor device is provided with a first and a second resistance elements whose one end is connected to a first node, a first protection element having a first terminal connected to the first wiring and a second terminal connected to the other end of the first resistance element, a second protection element having a third terminal connected to the other end of the second resistance element and a fourth terminal connected to the second wiring, and a third protection element having a fifth terminal connected to the first wiring and a sixth terminal connected to the second wiring.

公开(公告)号：US06476658B2

公开(公告)日：2002-11-05

申请号：US09847673

申请日：2001-05-02

申请人： Andre Schäfer

发明人： Andre Schäfer

IPC分类号： H03K508

CPC分类号： G11C5/063

摘要： The circuit configuration, in particular a DRAM element, has a protection device for suppressing the formation and/or emission of a reflection signal caused by a received supply input signal. An active signal matching device is provided, with which it is possible to prevent the formation of a reflection signal by using the input signal.

摘要翻译： 电路结构，特别是DRAM元件，具有用于抑制由接收的电源输入信号引起的反射信号的形成和/或发射的保护装置。 提供了一种有源信号匹配装置，可以通过使用输入信号来防止形成反射信号。

公开(公告)号：US06472923B2

公开(公告)日：2002-10-29

申请号：US10100847

申请日：2002-03-19

申请人： Yasuyuki Morishita

发明人： Yasuyuki Morishita

IPC分类号： H03K508

CPC分类号： H01L27/0266 ,  H03F1/523

摘要： A semiconductor device is provided with a signal terminal, a high potential side power supply terminal, a low potential side power supply terminal, a first wiring connected to the high potential side power supply terminal, a second wiring connected to the low potential side power supply terminal, and an internal circuit to which power is supplied from the first and second wirings. Further the semiconductor device is provided with a first and a second resistance elements whose one end is connected to a first node, a first protection element having a first terminal connected to the first wiring and a second terminal connected to the other end of the first resistance element, a second protection element having a third terminal connected to the other end of the second resistance element and a fourth terminal connected to the second wiring, and a third protection element having a fifth terminal connected to the first wiring and a sixth terminal connected to the second wiring.

公开(公告)号：US06441670B1

公开(公告)日：2002-08-27

申请号：US09930413

申请日：2001-08-15

申请人： Terry C. Coughlin, Jr. ,  Joseph M. Milewski ,  Akio Miyoshi ,  Loc Khac Nguyen

发明人： Terry C. Coughlin, Jr. ,  Joseph M. Milewski ,  Akio Miyoshi ,  Loc Khac Nguyen

IPC分类号： H03K508

CPC分类号： H03K5/08 ,  H03K19/00315

摘要： Receiver circuit providing interface between a legacy system sourcing logic signals including high logic level signals at first voltage levels to semiconductor IC devices operating at second voltage levels, wherein the first voltage levels are greater than the second voltage levels. The receiver circuit comprises: a pass gate device receiving the input voltages including high level logic signals at first logic levels and translating the high logic level signals to an intermediate voltage level for output at a first circuit node, the intermediate voltage level being less than the first voltage level; a first inverter device for receiving the translated voltages at the intermediate voltage levels and inverting the voltages for output at a second circuit node, whereby high input logic level voltages are pulled down at the second node and low input logic level voltages are pulled up at the second node; a circuit element in series with the first inverter device for connecting the first inverter device to a voltage supply source that provides pulled up signals at the second voltage levels in response to low logic level input voltages; and, a circuit responsive to pulled down voltage at the second node for deactivating the first circuit element to thereby prevent leakage current to ground through the first inverter device. Stable switching of voltages is achieved at the second node in a manner that eliminates leakage current between the voltage supply source providing pulled up signals at the second voltage levels and the receiver input.

摘要翻译： 接收器电路提供传统系统之间的接口，逻辑信号包括在第一电压电平处的高逻辑电平信号到在第二电压电平工作的半导体IC器件，其中第一电压电平大于第二电压电平。 接收器电路包括：通过栅极器件，其接收包括处于第一逻辑电平的高电平逻辑信号的输入电压，并将高逻辑电平信号转换成中间电压电平以在第一电路节点处输出，所述中间电压电平小于 第一电压电平; 第一逆变器装置，用于接收处于中间电压电平的转换电压并使第二电路节点处的输出电压反相，从而在第二节点向下拉高输入逻辑电平电压，并在第二节点处将低输入逻辑电平电压拉高 第二节点 与所述第一逆变器装置串联的电路元件，用于将所述第一逆变器装置连接到电压源，所述电压源响应于低逻辑电平输入电压而以所述第二电压电平提供上拉信号; 以及响应于第二节点处的下拉电压的电路，用于停用第一电路元件，从而防止通过第一逆变器装置接地的漏电流。 在第二节点处实现稳定的电压切换，以消除在第二电压电平提供上拉信号的电压源和接收器输入之间的泄漏电流。

公开(公告)号：US06400204B1

公开(公告)日：2002-06-04

申请号：US09625871

申请日：2000-07-26

申请人： Paul Cooper Davis

发明人： Paul Cooper Davis

IPC分类号： H03K508

CPC分类号： H01L27/0255

摘要： An integrated circuit is disclosed in which a steering diode is coupled between an input bond pad and a ground bond pad. The steering diode is reverse biased when a voltage applied to the input bond pad exceeds the voltage at the ground bond pad. A circuit coupled between the input bond pad and the ground bond pad includes a transistor having a first electrode coupled the input bond pad and a second electrode coupled to the ground bond pad. There may be other circuit elements between the emitter and the ground bond pad. At least two series coupled diodes are coupled between the input bond pad and the ground bond pad. The at least two series coupled diodes provide ESD protection to the transistor and circuit coupled between the input bond pad and the ground bond pad.

摘要翻译： 公开了一种集成电路，其中转向二极管耦合在输入接合焊盘和接地焊盘之间。 当施加到输入接合焊盘的电压超过接地焊盘的电压时，转向二极管被反向偏置。 耦合在输入接合焊盘和接地焊盘之间的电路包括具有耦合输入接合焊盘的第一电极和耦合到接地焊盘的第二电极的晶体管。 发射极和接地焊盘之间可能有其他电路元件。 至少两个串联耦合二极管耦合在输入接合焊盘和接地焊盘之间。 至少两个串联耦合二极管为耦合在输入接合焊盘和接地焊盘之间的晶体管和电路提供ESD保护。