公开(公告)号：US4750181A

公开(公告)日：1988-06-07

申请号：US927212

申请日：1986-11-05

申请人： Mark A. McDonald ,  Michael A. Zeeff

发明人： Mark A. McDonald ,  Michael A. Zeeff

IPC分类号： G06F11/00 ,  G06F11/16 ,  G11C29/00 ,  H04J3/06 ,  H04J3/14 ,  G01R31/28

CPC分类号： G06F11/1608 ,  G06F11/0751 ,  G11C29/003 ,  H04J3/0626 ,  H04J3/14

摘要： The present invention relates to a checking circuit concept which determines the integrity of data passing through a further circuit to be checked such as an elastic buffer. The concept is based on the fact that a serial data stream entering an elastic buffer must exit the elastic buffer intact without bit errors. Since the bit delay through the elastic buffer is a variable, it becomes difficult to test bit integrity. The present invention determines the bit integrity by sampling and storing a sequential set of data entering the elastic buffer and successively comparing it to data exiting the buffer. If no errors are present, the stored input data will match the data exiting the elastic buffer within N bits where N equals the storage bit location size of the elastic buffer.

摘要翻译： 本发明涉及一种检查电路概念，其确定通过诸如弹性缓冲器的待检查的另外的电路的数据的完整性。 该概念基于以下事实：输入弹性缓冲器的串行数据流必须完全退出弹性缓冲器而没有位错误。 由于通过弹性缓冲器的位延迟是变量，所以测试位完整性变得困难。 本发明通过采样和存储进入弹性缓冲器的顺序数据集并连续地将其与离开缓冲器的数据进行比较来确定比特完整性。 如果没有错误，则所存储的输入数据将与在N个位中的弹性缓冲器之前的数据匹配，其中N等于弹性缓冲器的存储位位置大小。

公开(公告)号：US5390333A

公开(公告)日：1995-02-14

申请号：US963507

申请日：1992-10-20

申请人： Harley P. Pritt ,  Michael A. Zeeff ,  Paul A. Littlewood

发明人： Harley P. Pritt ,  Michael A. Zeeff ,  Paul A. Littlewood

IPC分类号： G06F1/32 ,  H04Q11/08

CPC分类号： G06F1/3228 ,  G06F1/3203 ,  G06F1/3275 ,  H04Q11/08 ,  Y02B60/1228

摘要： In a multinode switch array, the maximum number of nodes that can be passing data from input to output lead can be no greater than the number of output leads in the array. Thus, the remaining nodes, while not performing a useful switch function, when implemented in CMOS (complementary metal oxide semiconductor), are consuming power due to changing logic levels in the circuitry and are causing the input data drivers to consume power due to the loading effect of the non-functional but actively connected nodes. The present invention overcomes these prior art disadvantages by ascertaining from the indirect address data stored in connect memory of each node, the times that the traffic memory needs to be activated and deactivates the memory and any associated driver at all other times in a manner such that it and the data driver are not consuming power incurred by data transfer operations.

摘要翻译： 在多节点开关阵列中，可以将数据从输入引脚传送到输出引线的最大节点数不得大于阵列中的输出引线数。 因此，当在CMOS（互补金属氧化物半导体）中实现时，剩余的节点在不执行有用的开关功能的同时由于电路中的逻辑电平的改变而消耗功率，并导致输入数据驱动器由于负载而消耗功率 非功能但主动连接的节点的效果。 本发明通过从存储在每个节点的连接存储器中的间接地址数据确定业务存储器需要被激活的时间以及在所有其他时间停止存储器和任何相关联的驱动程序来克服这些现有技术的缺点，其方式使得 它和数据驱动程序不会消耗数据传输操作所带来的电力。