公开(公告)号：US20150229528A1

公开(公告)日：2015-08-13

申请号：US14176908

申请日：2014-02-10

申请人： Gerard L. Swinkels ,  James Harley ,  David W. Boertjes ,  David Miedema ,  Michel Belanger ,  Paul A. Littlewood

发明人： Gerard L. Swinkels ,  James Harley ,  David W. Boertjes ,  David Miedema ,  Michel Belanger ,  Paul A. Littlewood

IPC分类号： H04L12/24 ,  H04Q11/00

CPC分类号： H04L41/0896 ,  H04B10/40 ,  H04J14/0257 ,  H04J14/0271 ,  H04L41/5025 ,  H04L41/5054 ,  H04Q11/0066 ,  H04Q2011/0086

摘要： A method, a network element, and a network include determining excess margin relative to margin needed to insure performance at a nominal guaranteed rate associated with a flexible optical modem configured to communicate over an optical link; causing the flexible optical modem to consume most or all of the excess margin, wherein the capacity increased above the nominal guaranteed rate includes excess capacity; and mapping the excess capacity to one or more logical interfaces for use by a management system, management plane, and/or control plane. The logical interfaces can advantageously be used by the management system, management plane, and/or control plane as one of restoration bandwidth or short-lived bandwidth-on-demand (BOD) connections, such as sub-network connections (SNCs) or label switched paths (LSPs).

摘要翻译： 一种方法，网络元件和网络包括确定相对于保证与被配置为通过光学链路通信的柔性光学调制解调器相关联的标称保证速率的性能所需的余量; 导致柔性光调制解调器消耗大部分或所有超额余量，其中增加到额定保证率以上的容量包括过剩容量; 并将剩余容量映射到一个或多个逻辑接口以供管理系统，管理平面和/或控制平面使用。 逻辑接口可以被管理系统，管理平面和/或控制平面有利地用作恢复带宽或短期带宽点播（BOD）连接之一，例如子网络连接（SNC）或标签 交换路径（LSP）。

公开(公告)号：US4764921A

公开(公告)日：1988-08-16

申请号：US797264

申请日：1985-11-12

申请人： Alan F. Graves ,  Paul A. Littlewood ,  Johannes S. Weiss

发明人： Alan F. Graves ,  Paul A. Littlewood ,  Johannes S. Weiss

IPC分类号： H04J3/00 ,  H04J3/06 ,  H04J3/08 ,  H04J3/12 ,  H04J3/16 ,  H04Q11/04 ,  H04Q11/08

CPC分类号： H04Q11/08 ,  H04J3/0602 ,  H04J3/08 ,  H04J3/12 ,  H04J3/1611

摘要： A multiplexed bit stream consists of interleaved words all of the same number of bits, the words corresponding to respective channels one of which is a synchronizing channel. A predetermined one of the bits of the words is used to identify the synchronizing channel, and may be used in the other, information, channels to carry service-related overhead and signalling information. The bit rate of the multiplexed bit stream is a harmonic of the bit rate of the individual channels. Such but streams can be further multiplexed together in a word-interleaved harmonic manner, whereby a harmonic structure of signals at different levels of multiplexing is built up.

摘要翻译： 复用的位流由相同位数的交织字组成，这些字对应于各自的信道，其中一个是同步信道。 字的预定的一个比特用于识别同步信道，并且可以在另一个信息中使用信道来承载业务相关开销和信令信息。 复用位流的比特率是各个信道的比特率的谐波。 这样的流可以以字交错谐波方式进一步多路复用，由此建立了不同复用级别的信号的谐波结构。

公开(公告)号：US4698806A

公开(公告)日：1987-10-06

申请号：US821931

申请日：1986-01-24

申请人： Alan F. Graves ,  Paul A. Littlewood

发明人： Alan F. Graves ,  Paul A. Littlewood

IPC分类号： H04J3/06

CPC分类号： H04J3/0602 ,  H04J3/0629

摘要： A frame alignment method and apparatus are disclosed for aligning the t.d.m. frames of tributaries, each including channel bytes synchronously multiplexed with a frame synchronizing byte, which are byte-interleaved to form overall t.d.m. frames identified by a frame synchronizing word, the tributaries having arbitrary frame phases with respect to one another. A channel counter is reset in response to the frame synchronizing word, and for each tributary in response to the frame synchronizing byte the count of the channel counter is used to determine an offset value which is stored in a memory. Each byte of each tributary is stored in a RAM at an address determined by substracting the respective tributary offset from the current count of the channel counter, whereby the tributaries are stored in the RAM in a frame-aligned manner. Reading of the tributary bytes can be effected sequentially or via a connection memory providing a time switching function.

摘要翻译： 公开了一种用于对准t.d.m.的框架对准方法和装置。 支路帧，每个包括与帧同步字节同步多路复用的信道字节，它们被字节交织以形成整体t.d.m。 由帧同步字识别的帧，支路相对于彼此具有任意的帧相位。 通道计数器响应于帧同步字复位，并且响应于帧同步字节对于每个支路，使用通道计数器的计数来确定存储在存储器中的偏移值。 每个支路的每个字节通过从通道计数器的当前计数中减去相应的支路偏移而确定的地址存储在RAM中，由此支路以帧对齐的方式存储在RAM中。 可以顺序地或经由提供时间切换功能的连接存储器来实现支路字节的读取。

公开(公告)号：US4622666A

公开(公告)日：1986-11-11

申请号：US680436

申请日：1984-12-10

申请人： Alan F. Graves ,  Paul A. Littlewood ,  Johannes S. Weiss

发明人： Alan F. Graves ,  Paul A. Littlewood ,  Johannes S. Weiss

IPC分类号： H04J3/06

CPC分类号： H04J3/0617

摘要： A framing circuit is disclosed for detecting framing bits in a t.d.m. bit stream having an extended DS1 framing format. The circuit comprises a RAM for storing in respect of each of the 772 time channels the five most recent information bits of the time channel and three other, candidate, bits which represent the likelihood that the particular time channel carries the framing bit pattern. The current and five stored information bits of each time channel are checked to detect the six-bit framing bit pattern. The candidate bits have their value increased or decreased, within predetermined limits, in dependence upon whether or not a phase of the framing bit pattern is detected, and the updated information and candidate bits are stored in the RAM. The modification of the candidate bits in this manner is effected in only every third 772-bit frame. A framing signal is produced in dependence upon the candidate bits.

摘要翻译： 公开了一种用于检测t.d.m中的成帧位的成帧电路。 具有扩展的DS1成帧格式的比特流。 该电路包括RAM，用于存储772个时间通道中的每一个时钟信道的五个最新信息位以及表示特定时间信道携带成帧位模式的可能性的三个其他候选位。 检查每个时间通道的当前和五个存储的信息位以检测六位成帧位模式。 根据是否检测到成帧位模式的相位，并且更新的信息和候选比特存储在RAM中，候选比特在其预定限制内增加或减少其值。 以这种方式对候选比特的修改仅在每第三个772比特帧中实现。 根据候选位产生成帧信号。

公开(公告)号：US5390333A

公开(公告)日：1995-02-14

申请号：US963507

申请日：1992-10-20

申请人： Harley P. Pritt ,  Michael A. Zeeff ,  Paul A. Littlewood

发明人： Harley P. Pritt ,  Michael A. Zeeff ,  Paul A. Littlewood

IPC分类号： G06F1/32 ,  H04Q11/08

CPC分类号： G06F1/3228 ,  G06F1/3203 ,  G06F1/3275 ,  H04Q11/08 ,  Y02B60/1228

摘要： In a multinode switch array, the maximum number of nodes that can be passing data from input to output lead can be no greater than the number of output leads in the array. Thus, the remaining nodes, while not performing a useful switch function, when implemented in CMOS (complementary metal oxide semiconductor), are consuming power due to changing logic levels in the circuitry and are causing the input data drivers to consume power due to the loading effect of the non-functional but actively connected nodes. The present invention overcomes these prior art disadvantages by ascertaining from the indirect address data stored in connect memory of each node, the times that the traffic memory needs to be activated and deactivates the memory and any associated driver at all other times in a manner such that it and the data driver are not consuming power incurred by data transfer operations.

摘要翻译： 在多节点开关阵列中，可以将数据从输入引脚传送到输出引线的最大节点数不得大于阵列中的输出引线数。 因此，当在CMOS（互补金属氧化物半导体）中实现时，剩余的节点在不执行有用的开关功能的同时由于电路中的逻辑电平的改变而消耗功率，并导致输入数据驱动器由于负载而消耗功率 非功能但主动连接的节点的效果。 本发明通过从存储在每个节点的连接存储器中的间接地址数据确定业务存储器需要被激活的时间以及在所有其他时间停止存储器和任何相关联的驱动程序来克服这些现有技术的缺点，其方式使得 它和数据驱动程序不会消耗数据传输操作所带来的电力。

公开(公告)号：US4876682A

公开(公告)日：1989-10-24

申请号：US862730

申请日：1986-05-13

申请人： Alan F. Graves ,  Paul A. Littlewood ,  Johannes S. Weiss

发明人： Alan F. Graves ,  Paul A. Littlewood ,  Johannes S. Weiss

IPC分类号： H04J3/08 ,  H04J3/16 ,  H04Q11/08

CPC分类号： H04Q11/08 ,  H04J3/08 ,  H04J3/1611

摘要： Digital signals are multiplexed in tdm (time division multiplex) frames each consisting of an integral number of sub-frames each consisting of an integral number of sub-sub-frames, whereby the tdm frame, sub-frame, and sub-sub-frame periods are harmonically related. The signals are switched in a hierarchy of time switches which are operated sequentially and cyclically with frame periods corresponding to respective ones of these harmonically related periods, whereby the switches switch services at respective harmonically related bandwidths. The harmonic tdm frame structure and the hierarchical switch arrangement combine to facilitate the switching of many services with various bandwidths using relatively small switches.

摘要翻译： 数字信号在tdm（时分复用）帧中被复用，每帧由整数个子帧组成，每个子帧由整数个子子帧组成，由此tdm帧，子帧和子子帧 时期是和谐相关的。 这些信号按照与这些谐波相关周期中的相应周期对应的帧周期顺序地和周期性地操作的时间开关的层级切换，由此交换机以相应的谐波相关带宽切换业务。 谐波tdm帧结构和分层交换机布置结合起来，以便利用相对较小的交换机来切换具有各种带宽的许多业务。

公开(公告)号：US09258190B2

公开(公告)日：2016-02-09

申请号：US14176908

申请日：2014-02-10

申请人： Gerard L. Swinkels ,  James Harley ,  David W. Boertjes ,  David Miedema ,  Michel Belanger ,  Paul A. Littlewood

发明人： Gerard L. Swinkels ,  James Harley ,  David W. Boertjes ,  David Miedema ,  Michel Belanger ,  Paul A. Littlewood

IPC分类号： H04L12/24 ,  H04Q11/00

CPC分类号： H04L41/0896 ,  H04B10/40 ,  H04J14/0257 ,  H04J14/0271 ,  H04L41/5025 ,  H04L41/5054 ,  H04Q11/0066 ,  H04Q2011/0086

摘要： A method, a network element, and a network include determining excess margin relative to margin needed to insure performance at a nominal guaranteed rate associated with a flexible optical modem configured to communicate over an optical link; causing the flexible optical modem to consume most or all of the excess margin, wherein the capacity increased above the nominal guaranteed rate includes excess capacity; and mapping the excess capacity to one or more logical interfaces for use by a management system, management plane, and/or control plane. The logical interfaces can advantageously be used by the management system, management plane, and/or control plane as one of restoration bandwidth or short-lived bandwidth-on-demand (BOD) connections, such as sub-network connections (SNCs) or label switched paths (LSPs).

摘要翻译： 一种方法，网络元件和网络包括确定相对于保证与被配置为通过光学链路通信的柔性光学调制解调器相关联的标称保证速率的性能所需的余量; 导致柔性光调制解调器消耗大部分或所有超额余量，其中增加到额定保证率以上的容量包括过剩容量; 并将剩余容量映射到一个或多个逻辑接口以供管理系统，管理平面和/或控制平面使用。 逻辑接口可以被管理系统，管理平面和/或控制平面有利地用作恢复带宽或短期带宽点播（BOD）连接之一，例如子网络连接（SNC）或标签 交换路径（LSP）。