公开(公告)号：US4849995A

公开(公告)日：1989-07-18

申请号：US889375

申请日：1986-07-25

申请人： Hiroshi Takeo ,  Masanori Kajiwara ,  Michinobu Ohhata ,  Takao Moriya ,  Satoshi Takeda ,  Hiroshi Nakaide ,  Hiroshi Yamasaki ,  Toshinari Kunieda ,  Ikuo Washiyama

发明人： Hiroshi Takeo ,  Masanori Kajiwara ,  Michinobu Ohhata ,  Takao Moriya ,  Satoshi Takeda ,  Hiroshi Nakaide ,  Hiroshi Yamasaki ,  Toshinari Kunieda ,  Ikuo Washiyama

IPC分类号： H04J3/06 ,  H04L7/04

CPC分类号： H04J3/0608 ,  H04L7/048

摘要： A digital signal transmission system includes a synchronization pattern detection circuit for detecting a synchronization pattern in response to a received transmitted digital signal, a pseudo synchronization detection circuit for detecting a pseudo synchronization pattern in the form of cyclic redundancy code in response to a received transmitted digital signal, and a synchronization protection circuit for counting the synchronization pattern detection signals produced when synchronization patterns are detected in response to a synchronization pattern detection signal from the synchronization pattern detection circuit. The synchronization protection circuit includes a main synchronization counter circuit and an auxiliary synchronization counter circuit. The count of protection steps for the confirmation of synchronization recovery of the auxiliary synchronization counter circuit in accordance with synchronization or asynchronization of the main synchronization counter circuit is variable.

摘要翻译： 数字信号传输系统包括：响应于所接收的发送的数字信号来检测同步模式的同步模式检测电路;伪同步检测电路，用于响应于所接收的发送的数字信号，以循环冗余码的形式检测伪同步模式 信号和同步保护电路，用于对来自同步模式检测电路的同步模式检测信号进行检测同步模式时产生的同步模式检测信号进行计数。 同步保护电路包括主同步计数器电路和辅助同步计数器电路。 根据主同步计数器电路的同步或异步确认辅助同步计数器电路的同步恢复的保护步骤的计数是可变的。

公开(公告)号：US4393318A

公开(公告)日：1983-07-12

申请号：US154949

申请日：1980-05-30

申请人： Masayuki Takahashi ,  Kunihiko Goto ,  Hisami Tanaka ,  Michinobu Ohhata

发明人： Masayuki Takahashi ,  Kunihiko Goto ,  Hisami Tanaka ,  Michinobu Ohhata

IPC分类号： G11C27/02 ,  H03K17/687

CPC分类号： G11C27/02

摘要： A sample and hold circuit for holding a sampled voltage, having a first MOS transistor for sampling the input voltage and a holding capacitor for holding the sampled voltage, and further comprising a second MOS transistor. The source and the drain of the second transistor are both connected to the output terminal of the circuit. The gate-source capacitance of the first MOS transistor is the sum of the gate-source and gate-drain capacitances of the second MOS transistor. When a voltage for turning on or off the first MOS transistor is applied to the gate of the first MOS transistor, the second MOS transistor is turned off or on respectively. The effect of this invention is that the sampled voltage can be held constant while turning off the first MOS transistor.

摘要翻译： 一种用于保持采样电压的采样和保持电路，具有用于对输入电压进行采样的第一MOS晶体管和用于保持采样电压的保持电容器，还包括第二MOS晶体管。 第二晶体管的源极和漏极都连接到电路的输出端子。 第一MOS晶体管的栅极 - 源极电容是第二MOS晶体管的栅极 - 源极和栅极 - 漏极电容的总和。 当将第一MOS晶体管的导通或截止电压施加到第一MOS晶体管的栅极时，第二MOS晶体管分别关断或接通。 本发明的效果是，在关闭第一MOS晶体管的同时，采样电压可以保持恒定。

公开(公告)号：US4377759A

公开(公告)日：1983-03-22

申请号：US227094

申请日：1980-12-19

申请人： Michinobu Ohhata ,  Toshihiko Matsumura ,  Masao Yamasawa ,  Takafumi Chujo ,  Masayuki Takahashi

发明人： Michinobu Ohhata ,  Toshihiko Matsumura ,  Masao Yamasawa ,  Takafumi Chujo ,  Masayuki Takahashi

IPC分类号： H03M1/00 ,  H03K5/08 ,  H03F1/34

CPC分类号： H04L25/064 ,  H03M1/0602

摘要： An offset compensating circuit is disclosed. The offset compensating circuit is inserted in a negative feedback loop of a circuit to be compensated and includes an integration circuit. The integration circuit includes a switching means mechanism and a switched capacitor type integrator. Said switching means mechanism produces either a positive reference voltage or a negative reference voltage in accordance with the polarity of the output signal of the circuit to be compensated. The positive or negative reference voltage is applied to the switched capacitor type integrator, which produces a compensating voltage signal to be combined with the input signal of the circuit to be compensated.

摘要翻译： PCT No.PCT / JP80 / 00084 Sec。 371日期1980年12月25日第 102（e）1980年12月19日PCT PCT申请日，1980年4月23日PCT公布。 出版物WO80 / 02347 日期为1980年10月30日。公开了偏移补偿电路。 偏移补偿电路被插入待补偿的电路的负反馈回路中并且包括积分电路。 集成电路包括开关装置机构和开关电容器型积分器。 所述开关装置机构根据待补偿电路的输出信号的极性产生正参考电压或负参考电压。 正或负参考电压被施加到开关电容器类型积分器，其产生要与要补偿的电路的输入信号组合的补偿电压信号。

公开(公告)号：US4337459A

公开(公告)日：1982-06-29

申请号：US150679

申请日：1980-05-16

申请人： Masauki Takahasi ,  Hisami Tanaka ,  Masao Yamasawa ,  Michinobu Ohhata

发明人： Masauki Takahasi ,  Hisami Tanaka ,  Masao Yamasawa ,  Michinobu Ohhata

IPC分类号： H03M1/74 ,  H03M1/00 ,  H03K13/02

CPC分类号： H03M1/802

摘要： A digital-to-analog converter of the capacitive voltage divider type, which comprises an output conductor, a ground conductor, a power source conductor, an array of capacitors and an array of switches connected between said output conductor and either the ground conductor or the power source conductor, and which provides a high impedance element connected between said output conductor and the ground conductor.

摘要翻译： 一种电容式分压器型数模转换器，其包括输出导体，接地导体，电源导体，电容器阵列和连接在所述输出导体和接地导体或接地导体之间的开关阵列 电源导体，并且其提供连接在所述输出导体和接地导体之间的高阻抗元件。

公开(公告)号：US4346476A

公开(公告)日：1982-08-24

申请号：US152556

申请日：1980-05-23

申请人： Masao Yamasawa ,  Michinobu Ohhata ,  Toshi Ikezawa

发明人： Masao Yamasawa ,  Michinobu Ohhata ,  Toshi Ikezawa

IPC分类号： H03M1/02 ,  H04B14/04 ,  H04L7/00 ,  H04L7/04

CPC分类号： H04B14/04

摘要： A codec, utilized for an PCM transmission system, has an a/d and d/a converter, and a digital phase locked loop circuit. The digital phase locked loop circuit generates internal operation clocks, which are used for the a/d and d/a converting operations, by dividing the frequency of the applied external clocks by a value determined in accordance with the frequency ratio between frame pulses and the external clocks.

摘要翻译： 用于PCM传输系统的编解码器具有a / d和d / a转换器和数字锁相环电路。 数字锁相环电路产生用于a / d和d / a转换操作的内部操作时钟，通过将施加的外部时钟的频率除以根据帧脉冲之间的频率比确定的值 外部时钟