公开(公告)号：US20120236671A1

公开(公告)日：2012-09-20

申请号：US13479065

申请日：2012-05-23

申请人： Eric CARMAN ,  Mikhail NAGOGA ,  Serguei OKHONIN

发明人： Eric CARMAN ,  Mikhail NAGOGA ,  Serguei OKHONIN

IPC分类号： G11C11/402

CPC分类号： G11C11/4096 ,  G11C11/406 ,  G11C2211/4016 ,  G11C2211/4065

摘要： A semiconductor device along with circuits including the same and methods of operating the same are described. The device comprises a memory cell including one transistor. The transistor comprises a gate, an electrically floating body region, and a source region and a drain region adjacent the body region. Data stored in memory cells of the device can be refreshed within a single clock cycle.

摘要翻译： 描述了包括其的电路的半导体器件及其操作方法。 该器件包括一个包括一个晶体管的存储单元。 晶体管包括栅极，电浮体区域，以及邻近身体区域的源极区域和漏极区域。 存储在设备的存储单元中的数据可以在单个时钟周期内刷新。

公开(公告)号：US07933142B2

公开(公告)日：2011-04-26

申请号：US11796935

申请日：2007-04-30

申请人： Serguei Okhonin ,  Mikhail Nagoga

发明人： Serguei Okhonin ,  Mikhail Nagoga

IPC分类号： G11C11/34

CPC分类号： G11C11/404 ,  G11C2211/4016 ,  H01L27/108 ,  H01L27/10802 ,  H01L29/7841

摘要： An integrated circuit device (for example, logic or discrete memory device) comprising a memory cell including a punch-through mode transistor, wherein the transistor includes a source region, a drain region, a gate, a gate insulator, and a body region having a storage node which is located, at least in part, immediately beneath the gate insulator. The memory cell includes at least two data states which are representative of an amount of charge in the storage node in the body region. First circuitry is coupled to the punch-through mode transistor of the memory cell to: (1) generate first and second sets of write control signals, and (2a) apply the first set of write control signals to the transistor to write a first data state in the memory cell and (2b) apply the second set of write control signals to the transistor to write a second data state in the memory cell. In response to the first set of write control signals, the punch-through mode transistor provides at least the first charge in the body region via impact ionization. The transistor may be disposed on a bulk-type substrate or SOI-type substrate.

摘要翻译： 一种集成电路器件（例如逻辑或分立存储器件），包括一个包括穿通型晶体管的存储单元，其中该晶体管包括一个源极区，一个漏极区，一个栅极，一个栅极绝缘体，以及一个具有 存储节点至少部分地位于栅极绝缘体的正下方。 存储单元包括代表身体区域中的存储节点中的电荷量的至少两个数据状态。 第一电路耦合到存储单元的穿通模式晶体管，以：（1）产生第一和第二组写入控制信号，以及（2a）将第一组写入控制信号施加到晶体管以写入第一数据 状态，并且（2b）将第二组写入控制信号施加到晶体管以在存储器单元中写入第二数据状态。 响应于第一组写入控制信号，穿通模式晶体管经由冲击电离至少提供身体区域中的第一电荷。 晶体管可以设置在体型衬底或SOI型衬底上。

公开(公告)号：US07606066B2

公开(公告)日：2009-10-20

申请号：US11509188

申请日：2006-08-24

申请人： Serguei Okhonin ,  Mikhail Nagoga

发明人： Serguei Okhonin ,  Mikhail Nagoga

IPC分类号： G11C11/34

CPC分类号： G11C11/409 ,  G11C11/404 ,  G11C11/4067 ,  G11C11/4076 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/1203 ,  H01L29/7841

摘要： A technique of writing, programming, holding, maintaining, sampling, sensing, reading and/or determining the data state of a memory cell of a memory cell array (for example, a memory cell array having a plurality of memory cells which consist of an electrically floating body transistor). In one aspect, the present inventions are directed to techniques to control and/or operate a semiconductor memory cell (and memory cell array having a plurality of such memory cells as well as an integrated circuit device including a memory cell array) having one or more electrically floating body transistors in which an electrical charge is stored in the body region of the electrically floating body transistor. The techniques of the present inventions may employ bipolar transistor currents to control, write and/or read a data state in such a memory cell. In this regard, the present inventions may employ a bipolar transistor current to control, write and/or read a data state in/of the electrically floating body transistor of the memory cell.

摘要翻译： 写入，编程，保持，维护，采样，感测，读取和/或确定存储器单元阵列的存储器单元的数据状态（例如，具有多个存储器单元的存储器单元阵列的技术） 电浮体晶体管）。 一方面，本发明涉及用于控制和/或操作半导体存储单元（以及具有多个这样的存储单元的存储单元阵列以及包括存储单元阵列的集成电路器件）的技术，该半导体存储单元具有一个或多个 电浮动体晶体管，其中电荷存储在电浮体晶体管的体区中。 本发明的技术可以采用双极晶体管电流来控制，写入和/或读取这种存储单元中的数据状态。 在这方面，本发明可以采用双极晶体管电流来控制，写入和/或读取存储单元的电浮体晶体管中的数据状态。

公开(公告)号：US10342493B2

公开(公告)日：2019-07-09

申请号：US14127727

申请日：2012-06-26

申请人： Christopher Elliott ,  Mark-Eric Jones ,  Mark Bennett ,  Mikhail Nagoga

发明人： Christopher Elliott ,  Mark-Eric Jones ,  Mark Bennett ,  Mikhail Nagoga

IPC分类号： A61B5/00 ,  A61B5/026 ,  A61B5/022 ,  A61B5/0205 ,  A61B5/0404 ,  A61B5/1455 ,  A61B5/021 ,  A61B5/145 ,  G01K13/00 ,  A61B7/02 ,  A61B8/06 ,  A61B5/01

摘要： The present invention provides a personal hand-held monitor comprising a signal acquisition device for acquiring signals which can be used to derive a measurement of a parameter related to the health of the user, the signal acquisition device being integrated with a personal hand-held computing device. The present invention also provides a signal acquisition device adapted to be integrated with a personal hand-held computing device to produce a personal hand-held monitor as defined above.

公开(公告)号：US08194487B2

公开(公告)日：2012-06-05

申请号：US12212326

申请日：2008-09-17

申请人： Eric Carman ,  Mikhail Nagoga ,  Serguei Okhonin

发明人： Eric Carman ,  Mikhail Nagoga ,  Serguei Okhonin

IPC分类号： G11C7/00

CPC分类号： G11C11/4096 ,  G11C11/406 ,  G11C2211/4016 ,  G11C2211/4065

摘要： A semiconductor device along with circuits including the same and methods of operating the same are described. The device comprises a memory cell including one transistor. The transistor comprises a gate, an electrically floating body region, and a source region and a drain region adjacent the body region. Data stored in memory cells of the device can be refreshed within a single clock cycle.

摘要翻译： 描述了包括其的电路的半导体器件及其操作方法。 该器件包括一个包括一个晶体管的存储单元。 晶体管包括栅极，电浮体区域，以及邻近身体区域的源极区域和漏极区域。 存储在设备的存储单元中的数据可以在单个时钟周期内刷新。

公开(公告)号：US20090201723A1

公开(公告)日：2009-08-13

申请号：US12367154

申请日：2009-02-06

申请人： Serguei Okhonin ,  Mikhail Nagoga

发明人： Serguei Okhonin ,  Mikhail Nagoga

IPC分类号： G11C11/34 ,  G11C11/416 ,  G11C7/00

CPC分类号： G11C11/406 ,  G11C11/404 ,  G11C2211/4016

摘要： A semiconductor device along with circuits including the same and methods of operating the same are described. The device comprises a memory cell including one transistor. The transistor comprises a gate, an electrically floating body region, and a source region and a drain region adjacent the body region. Data stored in memory cells of the device is inherently refreshed during hold operations.

摘要翻译： 描述了包括其的电路的半导体器件及其操作方法。 该器件包括一个包括一个晶体管的存储单元。 晶体管包括栅极，电浮体区域，以及邻近身体区域的源极区域和漏极区域。 存储在设备的存储单元中的数据在保持操作期间被固有地刷新。

公开(公告)号：US20080025083A1

公开(公告)日：2008-01-31

申请号：US11906036

申请日：2007-09-28

申请人： Serguei Okhonin ,  Mikhail Nagoga

发明人： Serguei Okhonin ,  Mikhail Nagoga

IPC分类号： G11C11/34

CPC分类号： G11C11/404 ,  G11C11/4076 ,  G11C2211/4016 ,  H01L27/1023 ,  H01L27/108 ,  H01L29/78 ,  H01L29/7841

摘要： A technique of sampling, sensing, reading and/or determining the data state of a memory cell (of, for example, a memory cell array) including an electrically floating body transistor. In this regard, the intrinsic bipolar transistor current component is employed to read and/or determine the data state of the electrically floating body memory cell. During the read operation, the data state is determined primarily by or read (or sensed) substantially using the bipolar current component responsive to the read control signals and significantly less by the interface channel current component, which is negligible relative to the bipolar component. The bipolar transistor current component may be very sensitive to the floating body potential due to the high gain of the intrinsic bipolar transistor of the electrically floating body transistor. As such, the programming window obtainable with this reading technique may be considerably higher than the programming window employing a conventional reading technique (which is based primarily on the interface channel current component).

摘要翻译： 一种采样，感测，读取和/或确定包括电浮体晶体管的存储单元（例如，存储单元阵列）的数据状态的技术。 在这方面，使用本征双极晶体管电流分量来读取和/或确定电浮体存储单元的数据状态。 在读取操作期间，数据状态主要由读取的控制信号基本上使用双极电流分量或相对于双极组件可忽略的界面通道电流分量来显着地（或感测到的）来确定或读取（或感测到的）数据状态。 由于电浮体晶体管的本征双极晶体管的高增益，双极晶体管电流分量可能对浮体电位非常敏感。 因此，利用该读取技术可获得的编程窗口可以比使用常规读取技术（其主要基于接口通道电流分量）的编程窗口高得多。

公开(公告)号：US20070023833A1

公开(公告)日：2007-02-01

申请号：US11453594

申请日：2006-06-15

申请人： Serguei Okhonin ,  Mikhail Nagoga

发明人： Serguei Okhonin ,  Mikhail Nagoga

IPC分类号： H01L27/12

CPC分类号： H01L29/7841 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10826 ,  H01L29/785

摘要： An integrated circuit device (for example, logic or discrete memory device) including a memory cell including an electrically floating body transistor, wherein the electrically floating body transistor includes a source region, a drain region, a body region disposed between the source region and the drain region, wherein the body region is electrically floating, and a gate disposed over the body region. The memory cell includes (i) a first data state which is representative of a first charge in the body region of the electrically floating body transistor, and (ii) a second data state which is representative of a second charge in the body region of the electrically floating body transistor. Circuitry, coupled to the electrically floating body transistor of the memory cell, (i) generates read control signals to perform a read operation of the memory cell and (ii) apply the read control signals to the electrically floating body transistor to sense the data state of the memory cell; wherein, in response to read control signals, the electrically floating body transistor replenishes charge in the body region of the electrically floating body transistor during the read operation. The electrically floating body transistor may be disposed on a bulk-type substrate or SOI-type substrate.

摘要翻译： 一种集成电路器件（例如，逻辑或分立存储器件），包括一个包括一电浮体晶体管的存储单元，其中该电浮体晶体管包括一源极区，一漏极区，置于源区和 漏极区域，其中所述体区域是电浮动的，以及设置在所述身体区域上的栅极。 存储单元包括（i）代表电浮体晶体管的体区中的第一电荷的第一数据状态，和（ii）代表在电浮体晶体管的体区中的第二电荷的第二数据状态 电浮体晶体管。 电路，耦合到存储单元的电浮体晶体管，（i）产生读控制信号以执行存储单元的读操作，和（ii）将读控制信号施加到电浮体晶体管以感测数据状态 的记忆单元; 其中，响应于读取控制信号，电浮动体晶体管在读操作期间补充电浮体晶体管的体区中的电荷。 电浮体晶体管可以设置在体型衬底或SOI型衬底上。

公开(公告)号：US20060098481A1

公开(公告)日：2006-05-11

申请号：US11247774

申请日：2005-10-11

申请人： Serguei Okhonin ,  Mikhail Nagoga

发明人： Serguei Okhonin ,  Mikhail Nagoga

IPC分类号： G11C11/34

CPC分类号： G11C11/4076 ,  G11C7/1045 ,  G11C29/02 ,  G11C29/026 ,  G11C29/028 ,  G11C2207/2254 ,  G11C2211/4016

摘要： An integrated circuit device comprising a memory array including a plurality of memory cells wherein each memory cell includes at least one electrically floating body transistor having a source region, a drain region, a body region disposed between the source region and the drain region, wherein the body region is electrically floating and a gate disposed over the body region and separated therefrom by a gate dielectric. Each memory cell includes a first data state representative of a first charge in the body region and a second data state representative of a second charge in the body region wherein the second charge is substantially provided by removing charge from the body region through the gate. The integrated circuit device further includes operating characteristics adjustment circuitry, coupled to the memory cell array, to responsively adjust one or more operating or response characteristics of one or more predetermined memory cells and thereby enhance the uniformity of operation or response of the predetermined memory cells of the memory array relative to the plurality of memory cells of the memory array.

摘要翻译： 一种集成电路装置，包括包括多个存储单元的存储器阵列，其中每个存储单元包括至少一个具有源极区，漏极区，设置在源区和漏区之间的体区的电浮体晶体管，其中， 身体区域是电浮动的，并且栅极设置在身体区域上并由栅极电介质分离。 每个存储单元包括表示体区中的第一电荷的第一数据状态和代表体区中的第二电荷的第二数据状态，其中第二电荷基本上通过从门体去除身体区域的电荷来提供。 集成电路装置还包括耦合到存储器单元阵列的操作特性调整电路，以响应地调整一个或多个预定存储器单元的一个或多个操作或响应特性，从而增强预定存储器单元的操作或响应的均匀性 存储器阵列相对于存储器阵列的多个存储器单元。

公开(公告)号：US08659948B2

公开(公告)日：2014-02-25

申请号：US13336805

申请日：2011-12-23

申请人： Serguei Okhonin ,  Mikhail Nagoga ,  Cedric Bassin

发明人： Serguei Okhonin ,  Mikhail Nagoga ,  Cedric Bassin

IPC分类号： G11C16/04

CPC分类号： G11C11/404 ,  G11C2211/4016 ,  H01L27/108 ,  H01L27/10802 ,  H01L29/7841

摘要： A semiconductor device along with circuits including the same and methods of operating the same are described. The device comprises a memory cell consisting essentially of one transistor. The transistor comprises a gate, an electrically floating body region, and a source region and a drain region adjacent the body region. The device includes data sense circuitry coupled to the memory cell. The data sense circuitry comprises a word line coupled to the gate region and a bit output coupled to the source region or the drain region.

摘要翻译： 描述了包括其的电路的半导体器件及其操作方法。 该器件包括基本上由一个晶体管组成的存储单元。 晶体管包括栅极，电浮体区域，以及邻近身体区域的源极区域和漏极区域。 该装置包括耦合到该存储单元的数据检测电路。 数据检测电路包括耦合到栅极区域的字线和耦合到源极区域或漏极区域的位输出。