公开(公告)号：US08659948B2

公开(公告)日：2014-02-25

申请号：US13336805

申请日：2011-12-23

Applicant: Serguei Okhonin ,  Mikhail Nagoga ,  Cedric Bassin

Inventor： Serguei Okhonin ,  Mikhail Nagoga ,  Cedric Bassin

IPC: G11C16/04

CPC classification number: G11C11/404 ,  G11C2211/4016 ,  H01L27/108 ,  H01L27/10802 ,  H01L29/7841

Abstract: A semiconductor device along with circuits including the same and methods of operating the same are described. The device comprises a memory cell consisting essentially of one transistor. The transistor comprises a gate, an electrically floating body region, and a source region and a drain region adjacent the body region. The device includes data sense circuitry coupled to the memory cell. The data sense circuitry comprises a word line coupled to the gate region and a bit output coupled to the source region or the drain region.

Abstract translation: 描述了包括其的电路的半导体器件及其操作方法。 该器件包括基本上由一个晶体管组成的存储单元。 晶体管包括栅极，电浮体区域，以及邻近身体区域的源极区域和漏极区域。 该装置包括耦合到该存储单元的数据检测电路。 数据检测电路包括耦合到栅极区域的字线和耦合到源极区域或漏极区域的位输出。

公开(公告)号：US20090016101A1

公开(公告)日：2009-01-15

申请号：US12130011

申请日：2008-05-30

Applicant: Serguei Okhonin ,  Mikhail Nagoga ,  Cedric Bassin

Inventor： Serguei Okhonin ,  Mikhail Nagoga ,  Cedric Bassin

IPC: G11C11/34

CPC classification number: G11C11/404 ,  G11C2211/4016 ,  H01L27/108 ,  H01L27/10802 ,  H01L29/7841

Abstract: A semiconductor device along with circuits including the same and methods of operating the same are described. The device comprises a memory cell consisting essentially of one transistor. The transistor comprises a gate, an electrically floating body region, and a source region and a drain region adjacent the body region. The device includes data sense circuitry coupled to the memory cell. The data sense circuitry comprises a word line coupled to the gate region and a bit output coupled to the source region or the drain region.

Abstract translation: 描述了包括其的电路的半导体器件及其操作方法。 该器件包括基本上由一个晶体管组成的存储单元。 晶体管包括栅极，电浮体区域，以及邻近身体区域的源极区域和漏极区域。 该装置包括耦合到该存储单元的数据检测电路。 数据检测电路包括耦合到栅极区域的字线和耦合到源极区域或漏极区域的位输出。

公开(公告)号：US08085594B2

公开(公告)日：2011-12-27

申请号：US12130011

申请日：2008-05-30

Applicant: Serguei Okhonin ,  Mikhail Nagoga ,  Cedric Bassin

Inventor： Serguei Okhonin ,  Mikhail Nagoga ,  Cedric Bassin

IPC: G11C11/34

CPC classification number: G11C11/404 ,  G11C2211/4016 ,  H01L27/108 ,  H01L27/10802 ,  H01L29/7841

Abstract: A semiconductor device along with circuits including the same and methods of operating the same are described. The device comprises a memory cell consisting essentially of one transistor. The transistor comprises a gate, an electrically floating body region, and a source region and a drain region adjacent the body region. The device includes data sense circuitry coupled to the memory cell. The data sense circuitry comprises a word line coupled to the gate region and a bit output coupled to the source region or the drain region.

Abstract translation: 描述了包括其的电路的半导体器件及其操作方法。 该器件包括基本上由一个晶体管组成的存储单元。 晶体管包括栅极，电浮体区域，以及邻近身体区域的源极区域和漏极区域。 该装置包括耦合到该存储单元的数据检测电路。 数据检测电路包括耦合到栅极区域的字线和耦合到源极区域或漏极区域的位输出。

公开(公告)号：US07933142B2

公开(公告)日：2011-04-26

申请号：US11796935

申请日：2007-04-30

Applicant: Serguei Okhonin ,  Mikhail Nagoga

Inventor： Serguei Okhonin ,  Mikhail Nagoga

IPC: G11C11/34

CPC classification number: G11C11/404 ,  G11C2211/4016 ,  H01L27/108 ,  H01L27/10802 ,  H01L29/7841

Abstract: An integrated circuit device (for example, logic or discrete memory device) comprising a memory cell including a punch-through mode transistor, wherein the transistor includes a source region, a drain region, a gate, a gate insulator, and a body region having a storage node which is located, at least in part, immediately beneath the gate insulator. The memory cell includes at least two data states which are representative of an amount of charge in the storage node in the body region. First circuitry is coupled to the punch-through mode transistor of the memory cell to: (1) generate first and second sets of write control signals, and (2a) apply the first set of write control signals to the transistor to write a first data state in the memory cell and (2b) apply the second set of write control signals to the transistor to write a second data state in the memory cell. In response to the first set of write control signals, the punch-through mode transistor provides at least the first charge in the body region via impact ionization. The transistor may be disposed on a bulk-type substrate or SOI-type substrate.

Abstract translation: 一种集成电路器件（例如逻辑或分立存储器件），包括一个包括穿通型晶体管的存储单元，其中该晶体管包括一个源极区，一个漏极区，一个栅极，一个栅极绝缘体，以及一个具有 存储节点至少部分地位于栅极绝缘体的正下方。 存储单元包括代表身体区域中的存储节点中的电荷量的至少两个数据状态。 第一电路耦合到存储单元的穿通模式晶体管，以：（1）产生第一和第二组写入控制信号，以及（2a）将第一组写入控制信号施加到晶体管以写入第一数据 状态，并且（2b）将第二组写入控制信号施加到晶体管以在存储器单元中写入第二数据状态。 响应于第一组写入控制信号，穿通模式晶体管经由冲击电离至少提供身体区域中的第一电荷。 晶体管可以设置在体型衬底或SOI型衬底上。

公开(公告)号：US07606066B2

公开(公告)日：2009-10-20

申请号：US11509188

申请日：2006-08-24

Applicant: Serguei Okhonin ,  Mikhail Nagoga

Inventor： Serguei Okhonin ,  Mikhail Nagoga

IPC: G11C11/34

CPC classification number: G11C11/409 ,  G11C11/404 ,  G11C11/4067 ,  G11C11/4076 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/1203 ,  H01L29/7841

Abstract: A technique of writing, programming, holding, maintaining, sampling, sensing, reading and/or determining the data state of a memory cell of a memory cell array (for example, a memory cell array having a plurality of memory cells which consist of an electrically floating body transistor). In one aspect, the present inventions are directed to techniques to control and/or operate a semiconductor memory cell (and memory cell array having a plurality of such memory cells as well as an integrated circuit device including a memory cell array) having one or more electrically floating body transistors in which an electrical charge is stored in the body region of the electrically floating body transistor. The techniques of the present inventions may employ bipolar transistor currents to control, write and/or read a data state in such a memory cell. In this regard, the present inventions may employ a bipolar transistor current to control, write and/or read a data state in/of the electrically floating body transistor of the memory cell.

Abstract translation: 写入，编程，保持，维护，采样，感测，读取和/或确定存储器单元阵列的存储器单元的数据状态（例如，具有多个存储器单元的存储器单元阵列的技术） 电浮体晶体管）。 一方面，本发明涉及用于控制和/或操作半导体存储单元（以及具有多个这样的存储单元的存储单元阵列以及包括存储单元阵列的集成电路器件）的技术，该半导体存储单元具有一个或多个 电浮动体晶体管，其中电荷存储在电浮体晶体管的体区中。 本发明的技术可以采用双极晶体管电流来控制，写入和/或读取这种存储单元中的数据状态。 在这方面，本发明可以采用双极晶体管电流来控制，写入和/或读取存储单元的电浮体晶体管中的数据状态。

公开(公告)号：US20110194363A1

公开(公告)日：2011-08-11

申请号：US13092704

申请日：2011-04-22

Applicant: Serguei Okhonin ,  Mikhail Nagoga

Inventor： Serguei Okhonin ,  Mikhail Nagoga

IPC: G11C7/00

CPC classification number: G11C11/404 ,  G11C2211/4016 ,  H01L27/108 ,  H01L27/10802 ,  H01L29/7841

Abstract: An integrated circuit device (for example, logic or discrete memory device) comprising a memory cell including a punch-through mode transistor, wherein the transistor includes a source region, a drain region, a gate, a gate insulator, and a body region having a storage node which is located, at least in part, immediately beneath the gate insulator. The memory cell includes at least two data states which are representative of an amount of charge in the storage node in the body region. First circuitry is coupled to the punch-through mode transistor of the memory cell to: (1) generate first and second sets of write control signals, and (2a) apply the first set of write control signals to the transistor to write a first data state in the memory cell and (2b) apply the second set of write control signals to the transistor to write a second data state in the memory cell. In response to the first set of write control signals, the punch-through mode transistor provides at least the first charge in the body region via impact ionization. The transistor may be disposed on a bulk-type substrate or SOI-type substrate.

Abstract translation: 一种集成电路器件（例如逻辑或分立存储器件），包括一个包括穿通型晶体管的存储器单元，其中该晶体管包括一个源极区，一个漏极区，一个栅极，一个栅极绝缘体以及一个具有 存储节点至少部分地位于栅极绝缘体的正下方。 存储单元包括代表身体区域中的存储节点中的电荷量的至少两个数据状态。 第一电路耦合到存储单元的穿通模式晶体管，以：（1）产生第一和第二组写入控制信号，以及（2a）将第一组写入控制信号施加到晶体管以写入第一数据 状态，并且（2b）将第二组写入控制信号施加到晶体管以在存储器单元中写入第二数据状态。 响应于第一组写入控制信号，穿通模式晶体管经由冲击电离至少提供身体区域中的第一电荷。 晶体管可以设置在体型衬底或SOI型衬底上。

公开(公告)号：US20100271857A1

公开(公告)日：2010-10-28

申请号：US12768322

申请日：2010-04-27

Applicant: Yogesh Luthra ,  Serguei Okhonin ,  Mikhail Nagoga

Inventor： Yogesh Luthra ,  Serguei Okhonin ,  Mikhail Nagoga

IPC: G11C5/06 ,  G11C7/00

CPC classification number: H01L27/0664 ,  G11C5/025 ,  G11C5/06 ,  G11C5/063 ,  G11C7/00 ,  G11C8/08 ,  G11C8/10 ,  G11C11/4074 ,  G11C11/4094 ,  G11C2211/4016 ,  H01L29/7302 ,  H01L29/732

Abstract: Techniques for providing a direct injection semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method for biasing a direct injection semiconductor memory device. The method may comprise applying a first voltage potential to a first N-doped region via a bit line and applying a second voltage potential to a second N-doped region via a source line. The method may also comprise applying a third voltage potential to a word line, wherein the word line is spaced apart from and capacitively coupled to a body region that is electrically floating and disposed between the first N-doped region and the second N-doped region. The method may further comprise applying a fourth voltage potential to a P-type substrate via a carrier injection line.

Abstract translation: 公开了提供直接注入半导体存储器件的技术。 在一个特定的示例性实施例中，可以将技术实现为用于偏置直接注入半导体存储器件的方法。 该方法可以包括经由位线将第一电压电势施加到第一N掺杂区域，并且经由源极线将第二电压电势施加到第二N掺杂区域。 该方法还可以包括将第三电压电位施加到字线，其中字线与电浮置并且设置在第一N掺杂区域和第二N掺杂区域之间的体区间隔开并且电容耦合 。 该方法还可以包括经由载体注入管线向P型衬底施加第四电压电位。

公开(公告)号：US20090080244A1

公开(公告)日：2009-03-26

申请号：US12212326

申请日：2008-09-17

Applicant: Eric Carman ,  Mikhail Nagoga ,  Serguei Okhonin

Inventor： Eric Carman ,  Mikhail Nagoga ,  Serguei Okhonin

IPC: G11C11/34

CPC classification number: G11C11/4096 ,  G11C11/406 ,  G11C2211/4016 ,  G11C2211/4065

Abstract: A semiconductor device along with circuits including the same and methods of operating the same are described. The device comprises a memory cell including one transistor. The transistor comprises a gate, an electrically floating body region, and a source region and a drain region adjacent the body region. Data stored in memory cells of the device can be refreshed within a single clock cycle.

Abstract translation: 描述了包括其的电路的半导体器件及其操作方法。 该器件包括一个包括一个晶体管的存储单元。 晶体管包括栅极，电浮体区域，以及邻近身体区域的源极区域和漏极区域。 存储在设备的存储单元中的数据可以在单个时钟周期内刷新。

公开(公告)号：US07477540B2

公开(公告)日：2009-01-13

申请号：US11906036

申请日：2007-09-28

Applicant: Serguei Okhonin ,  Mikhail Nagoga

Inventor： Serguei Okhonin ,  Mikhail Nagoga

IPC: G11C11/34

CPC classification number: G11C11/404 ,  G11C11/4076 ,  G11C2211/4016 ,  H01L27/1023 ,  H01L27/108 ,  H01L29/78 ,  H01L29/7841

Abstract: A technique of sampling, sensing, reading and/or determining the data state of a memory cell (of, for example, a memory cell array) including an electrically floating body transistor. In this regard, the intrinsic bipolar transistor current component is employed to read and/or determine the data state of the electrically floating body memory cell. During the read operation, the data state is determined primarily by or read (or sensed) substantially using the bipolar current component responsive to the read control signals and significantly less by the interface channel current component, which is negligible relative to the bipolar component. The bipolar transistor current component may be very sensitive to the floating body potential due to the high gain of the intrinsic bipolar transistor of the electrically floating body transistor. As such, the programming window obtainable with this reading technique may be considerably higher than the programming window employing a conventional reading technique (which is based primarily on the interface channel current component).

Abstract translation: 一种采样，感测，读取和/或确定包括电浮体晶体管的存储单元（例如，存储单元阵列）的数据状态的技术。 在这方面，使用本征双极晶体管电流分量来读取和/或确定电浮体存储单元的数据状态。 在读取操作期间，数据状态主要由读取的控制信号基本上使用双极电流分量或相对于双极组件可忽略的界面通道电流分量来显着地（或感测到的）来确定或读取（或感测到的）数据状态。 由于电浮体晶体管的本征双极晶体管的高增益，双极晶体管电流分量可能对浮体电位非常敏感。 因此，利用该读取技术可获得的编程窗口可以比使用常规读取技术（其主要基于接口通道电流分量）的编程窗口高得多。

公开(公告)号：US07301803B2

公开(公告)日：2007-11-27

申请号：US11304387

申请日：2005-12-15

Applicant: Serguei Okhonin ,  Mikhail Nagoga

Inventor： Serguei Okhonin ,  Mikhail Nagoga

IPC: G11C11/34

CPC classification number: G11C11/404 ,  G11C11/4076 ,  G11C2211/4016 ,  H01L27/1023 ,  H01L27/108 ,  H01L29/78 ,  H01L29/7841

Abstract: A method and a device for the coding and decoding of an information symbol for transmission over a transmission channel or a received signal value is described and illustrated, whereby a channel symbol used for coding is selected from at least two available channel symbols by means of a pre-calculated expected received signal value. The pre-calculation is achieved, based on the echo properties of the transmission channel and transmission values already sent. A pre-coding method with low receiver-side calculation requirement is thus prepared, whereby the information symbol can be transmitted by means of various channel symbols and thus various transmission values can also be transmitted. The possible selections may be used for minimization of the transmission energy and/or to achieve a minimal disturbance or even a constructive effect through the inter-symbol interference occurring on transmission.

Abstract translation: 描述和说明用于对传输信道或接收信号值进行传输的信息符号进行编码和解码的方法和装置，借此通过以下方式从至少两个可用信道符号中选择用于编码的信道符号： 预先计算的预期接收信号值。 基于传输信道的回波特性和已经发送的传输值，实现了预计算。 因此，准备了具有低接收机侧计算要求的预编码方法，由此可以通过各种信道符号发送信息符号，并且因此也可以发送各种传输值。 可能的选择可以用于最小化传输能量和/或通过在传输上发生的符号间干扰来实现最小的干扰或甚至是建设性的效果。