摘要:
There is provided a device and method for detecting an overlap of pulse signals, capable of easily detecting a point where reference and delayed pulse signals overlap each other, and an apparatus for estimating a distance using the same. The device for detecting an overlap of pulse signals, the device detecting a point where first and second pulse signals having different frequencies begin to overlap each other, the device including: a duty adjustor generating a third pulse signal by increasing a duty of the second pulse signal; a pulse signal calculator multiplying the first and second pulse signals by the third pulse signal, respectively and adding respective results together to output a signal; and an overlap determiner determining a middle of a pulse with a greatest width in the signal outputted from the pulse signal calculator as a point where the first and second pulse signals overlap each other.
摘要:
The present invention provides an MLCC and an MLCC array. The MLCC has desirably low ESL properties by forming the first and second internal electrodes to be spaced apart from each other on the same dielectric layer while overlapping with other first and second internal electrodes on the neighboring dielectric layers, and connecting the first and second internal electrodes to the external terminals provided on the top surface or the bottom surface of the capacitor body through conductive via holes formed in the capacitor body in a stacking direction of the capacitor body.
摘要:
Disclosed herein is a multilayered chip capacitor array, including a capacitor body having a plurality of dielectric layers, a plurality of pairs of first and second inner electrodes which are formed on the plurality of dielectric layers such that one electrode of one pair of inner electrodes faces the other electrode of the one pair of inner electrodes with one of the plurality of dielectric layers interposed therebetween, at least one first outer terminal and a plurality of second outer terminals formed on at least one surface of a top surface and a bottom surface of the capacitor body, and at least one first conductive via and a plurality of second conductive vias formed in a stacking direction of the capacitor body and connected to the first outer terminal and the second outer terminal, respectively.