公开(公告)号：US20110291714A1

公开(公告)日：2011-12-01

申请号：US12789453

申请日：2010-05-27

申请人： Peng-Fei Lin ,  Ming-Chi Lin ,  Po-Hao Yu

发明人： Peng-Fei Lin ,  Ming-Chi Lin ,  Po-Hao Yu

IPC分类号： H03L7/06

CPC分类号： H03L7/091

摘要： A phase-locked loop (PLL) with novel phase detection mechanism is provided, including a phase frequency detector (PFD), a controller, a digital-to-analog (D2A) module, and a voltage-controlled oscillator/current-controlled oscillator (VCO/ICO), wherein PFD has a reference signal input and an input from output signal of the VCO/ICO and is connected to the controller, the controller is then further connected to D2A module, D2A module converts the control signal from the controller into an analog voltage to control the frequency and phase of VCO/ICO. It is worth noting that the PFD of the present invention has a novel phase detection mechanism so that the phase detection does not rely on edge alignment. In addition, the novel phase detection mechanism also allows flexible reference signal input, as opposed to the aforementioned fixed external source, such as, a crystal.

摘要翻译： 提供了具有新型相位检测机构的锁相环（PLL），包括相位频率检测器（PFD），控制器，数模（D2A）模块和压控振荡器/电流控制振荡器 （VCO / ICO），其中PFD具有参考信号输入和来自VCO / ICO的输出信号的输入并且连接到控制器，然后控制器进一步连接到D2A模块，D2A模块将来自控制器的控制信号 转换成模拟电压，以控制VCO / ICO的频率和相位。 值得注意的是，本发明的PFD具有新的相位检测机构，使得相位检测不依赖于边缘对准。 此外，与上述固定外部源（例如晶体）相反，新型相位检测机构还允许灵活的参考信号输入。

公开(公告)号：US20080180181A1

公开(公告)日：2008-07-31

申请号：US11669944

申请日：2007-01-31

申请人： Ming-Hung Wang ,  Peng-Fei Lin ,  Ming-Chi Lin

发明人： Ming-Hung Wang ,  Peng-Fei Lin ,  Ming-Chi Lin

IPC分类号： H03B27/00

CPC分类号： H03B27/00 ,  H03K5/13 ,  H03K2005/00052

摘要： An apparatus for generating multi-phase clock signals with a ring oscillator is provided, including a first stage phase-blender module and a second stage phase-blender module. The first stage phase-blender module further includes a plurality of differential OP phase-blender circuits. Each differential blender circuit has two signal inputs, and an output signal whose phase is an interpolation of the two input signal. The second stage phase blender module includes a plurality of inverter phase-blender circuits. Each inverter phase-blender circuit receives two output signals from the first stage phase-blender module as inputs, and outputs a clock signal with the interpolated phase of the two output signals of the first stage phase-blender module. The present invention also provides a method for generating multi-phase clock signals with a ring oscillator, including the following steps: (1) using a ring oscillator to provide at least two non-full swing signals, (2) using an differential OP phase-blender circuit to blend the phases of two non-full signals from the ring oscillator, and (3) using an inverter phase-blender circuit to generate multi-phase clock signal with interpolated phase.

摘要翻译： 提供了一种用于产生具有环形振荡器的多相时钟信号的装置，包括第一级相位 - 混合器模块和第二级相位 - 混合器模块。 第一级相位 - 搅拌器模块还包括多个差动OP相 - 搅拌器回路。 每个差分式混合器电路都有两个信号输入端，一个输出信号的相位是两个输入信号的插值。 第二级相位混合器模块包括多个逆变器相位混合器电路。 每个逆变器相位混合器电路接收来自第一级相位 - 混合器模块的两个输出信号作为输入，并且输出具有第一级相位 - 混合器模块的两个输出信号的内插相位的时钟信号。 本发明还提供了一种用环形振荡器产生多相时钟信号的方法，包括以下步骤：（1）使用环形振荡器提供至少两个非全摆幅信号，（2）使用差分OP相位 混合来自环形振荡器的两个非满信号的相位，以及（3）使用逆变器相位混合器电路产生具有内插相位的多相时钟信号。

公开(公告)号：US06798704B2

公开(公告)日：2004-09-28

申请号：US10286857

申请日：2002-11-04

申请人： Hsing-Yi Chen ,  Ming Chi Lin

发明人： Hsing-Yi Chen ,  Ming Chi Lin

IPC分类号： G11C700

CPC分类号： G11C7/106 ,  G11C7/062 ,  G11C7/067 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/1066

摘要： A semiconductor memory with a sense amplifier for high-speed sensing of the signal from a memory cell. The semiconductor memory includes plural memory arrays having plural memory cells, a sense amplifier, and a latch circuit. The memory cells are precharged when a precharge signal is enabled. The sense amplifier has an additional discharge path enabled by the disabled precharge signal to speed up reading data. The latch circuit is turn off by the enabled precharged signal to hold the data.

摘要翻译： 一种具有读出放大器的半导体存储器，用于高速感测来自存储单元的信号。 半导体存储器包括具有多个存储单元的多个存储器阵列，读出放大器和锁存电路。 当预充电信号使能时，存储单元被预充电。 读出放大器具有由禁用的预充电信号使能的附加放电路径，以加速读取数据。 锁存电路由启用的预充电信号关闭以保持数据。

公开(公告)号：US06274466B1

公开(公告)日：2001-08-14

申请号：US09328967

申请日：1999-06-09

申请人： Chung-Po Hsu ,  Ming-Chi Lin

发明人： Chung-Po Hsu ,  Ming-Chi Lin

IPC分类号： H01L21336

CPC分类号： H01L21/26513 ,  H01L29/167

摘要： A method for fabricating a semiconductor device to increase the effective concentration of a doped region. A first dopant is implanted into a substrate. A second dopant is implanted into the substrate. The first dopant has a lower diffusion coefficient, a higher energy gap, and a higher atomic mass than those of the second dopant.

摘要翻译： 一种用于制造半导体器件以增加掺杂区域的有效浓度的方法。 将第一掺杂剂注入到衬底中。 将第二掺杂剂注入到衬底中。 第一掺杂剂具有比第二掺杂剂低的扩散系数，更高的能隙和更高的原子质量。

公开(公告)号：US07482884B2

公开(公告)日：2009-01-27

申请号：US11669944

申请日：2007-01-31

申请人： Ming-Hung Wang ,  Peng-Fei Lin ,  Ming-Chi Lin

发明人： Ming-Hung Wang ,  Peng-Fei Lin ,  Ming-Chi Lin

IPC分类号： H03B5/24 ,  H03B27/00 ,  H03K3/03

CPC分类号： H03B27/00 ,  H03K5/13 ,  H03K2005/00052

摘要： An apparatus for generating multi-phase clock signals with a ring oscillator is provided, including a first stage phase-blender module and a second stage phase-blender module. The first stage phase-blender module further includes a plurality of differential OP phase-blender circuits. Each differential blender circuit has two signal inputs, and an output signal whose phase is an interpolation of the two input signals. The second stage phase blender module includes a plurality of inverter phase-blender circuits. Each inverter phase-blender circuit receives two output signals from the first stage phase-blender module as inputs, and outputs a clock signal with the interpolated phase of the two output signals of the first stage phase-blender module.

摘要翻译： 提供了一种用于产生具有环形振荡器的多相时钟信号的装置，包括第一级相位 - 混合器模块和第二级相位 - 混合器模块。 第一级相位 - 搅拌器模块还包括多个差动OP相 - 搅拌器回路。 每个差分式混合器电路都有两个信号输入端，一个输出信号的相位是两个输入信号的插值。 第二级相位混合器模块包括多个逆变器相位混合器电路。 每个逆变器相位混合器电路接收来自第一级相位 - 混合器模块的两个输出信号作为输入，并且输出具有第一级相位 - 混合器模块的两个输出信号的内插相位的时钟信号。

公开(公告)号：US08350605B2

公开(公告)日：2013-01-08

申请号：US12789453

申请日：2010-05-27

申请人： Peng-Fei Lin ,  Ming-Chi Lin ,  Po-Hao Yu

发明人： Peng-Fei Lin ,  Ming-Chi Lin ,  Po-Hao Yu

IPC分类号： H03L7/06

CPC分类号： H03L7/091

摘要： A phase-locked loop (PLL) with novel phase detection mechanism is provided, including a phase frequency detector (PFD), a controller, a digital-to-analog (D2A) module, and a voltage-controlled oscillator/current-controlled oscillator (VCO/ICO), wherein PFD has a reference signal input and an input from the output signal of the VCO/ICO and is connected to the controller, the controller is then further connected to the D2A module, the D2A module converts the control signal from the controller into an analog voltage to control the frequency and phase of VCO/ICO. It is worth noting that the PFD of the present invention has a novel phase detection mechanism so that the phase detection can be accomplished by observing signal level transitions of the reference signal input and a delayed reference signal with respect to the output signal of the VCO/ICO without edge alignment. In addition, the novel phase detection mechanism also allows flexible reference signal input.

摘要翻译： 提供了具有新型相位检测机构的锁相环（PLL），包括相位频率检测器（PFD），控制器，数模（D2A）模块和压控振荡器/电流控制振荡器 （VCO / ICO），其中PFD具有参考信号输入和来自VCO / ICO的输出信号的输入并连接到控制器，然后控制器进一步连接到D2A模块，D2A模块将控制信号 从控制器进入模拟电压来控制VCO / ICO的频率和相位。 值得注意的是，本发明的PFD具有新颖的相位检测机制，使得可以通过观察参考信号输入的信号电平转换和相对于VCO / VCO的输出信号的延迟参考信号来实现相位检测。 ICO无边缘对齐。 此外，新颖的相位检测机构还允许灵活的参考信号输入。