摘要:
The present invention relates to a transistor comprising a gate channel area and a gate stack having mechanical stress arranged on the gate channel area.
摘要:
The present invention provides methods of producing substantially void-free trench structures. After deposition of an a-Si or polysilicon layer in a trench formed in a semiconductor, the a-Si or polysilicon is exposed to hydrogen at an elevated temperature.
摘要:
A method for manufacturing a trench capacitor uses a low-pressure gas phase doping for forming a buried plate as a capacitor plate. The use of the low-pressure gas phase doping reduces process costs and improves capacitor properties.
摘要:
The present invention provides a fabrication method for a semiconductor structure having the steps of providing a semiconductor substrate (1); providing and patterning a silicon nitride layer (3) on the semiconductor substrate (1) as topmost layer of a trench etching mask; forming a trench (5) in a first etching step by means of the trench etching mask; conformally depositing a liner layer (10) made of silicon oxide above the resulting structure, which leaves a gap (SP) reaching into the depth in the trench (5); carrying out a V plasma etching step for forming a V profile of the line layer (10) in the trench (5); wherein the liner layer (10) is pulled back to below the top side of the silicon nitride layer (3); an etching gas mixture comprises C5F8, O2 and an inert gas is used in the V plasma etching step; the ratio (V) of C5F8/O2 lies between 2.5 and 3.5; and the selectivity of the V plasma etching step between silicon oxide and silicon nitride is at least 10.
摘要翻译:本发明提供一种半导体结构的制造方法,其具有提供半导体衬底(1)的步骤。 在半导体衬底(1)上提供和图案化氮化硅层(3)作为沟槽蚀刻掩模的最顶层; 在第一蚀刻步骤中通过沟槽蚀刻掩模形成沟槽(5); 在所得结构上保形地沉积由氧化硅制成的衬垫层(10),留下在沟槽(5)中深入的间隙(SP); 执行V等离子体蚀刻步骤,用于在沟槽(5)中形成线层(10)的V轮廓; 其中所述衬垫层(10)被拉回到所述氮化硅层(3)的顶侧的下方; 蚀刻气体混合物包括C 5 C 8 O 2 O 2,在V等离子体蚀刻步骤中使用惰性气体; C 5 / C 2 O 2的比例(V)在2.5和3.5之间; 并且氧化硅和氮化硅之间的V等离子体蚀刻步骤的选择性为至少10。
摘要:
A method for improving a doping profile using gas phase doping is described. In the method, silicon nitride and/or products of decomposition from a silicon nitride deposition are introduced in a process chamber before or during the actual gas phase doping. This allows the doping profile to be significantly improved.
摘要:
The present invention provides a fabrication method for a semiconductor structure having the steps of providing a semiconductor substrate (1); providing and patterning a silicon nitride layer (3) on the semiconductor substrate (1) as topmost layer of a trench etching mask; forming a trench (5) in a first etching step by means of the trench etching mask; conformally depositing a liner layer (10) made of silicon oxide above the resulting structure, which leaves a gap (SP) reaching into the depth in the trench (5); carrying out a V plasma etching step for forming a V profile of the line layer (10) in the trench (5); wherein the liner layer (10) is pulled back to below the top side of the silicon nitride layer (3); an etching gas mixture comprises C5F8, O2 and an inert gas is used in the V plasma etching step; the ratio (V) of C5F8/O2 lies between 2.5 and 3.5; and the selectivity of the V plasma etching step between silicon oxide and silicon nitride is at least 10.
摘要翻译:本发明提供一种半导体结构的制造方法,其具有提供半导体衬底(1)的步骤。 在半导体衬底(1)上提供和图案化氮化硅层(3)作为沟槽蚀刻掩模的最顶层; 在第一蚀刻步骤中通过沟槽蚀刻掩模形成沟槽(5); 在所得结构上保形地沉积由氧化硅制成的衬垫层(10),留下在沟槽(5)中深入的间隙(SP); 进行用于在沟槽(5)中形成线层(10)的V轮廓的V等离子体蚀刻步骤; 其中所述衬垫层(10)被拉回到所述氮化硅层(3)的顶侧的下方; 蚀刻气体混合物包括C 5 C 8 O 2 O 2,在V等离子体蚀刻步骤中使用惰性气体; C 5 / C 2 O 2的比例(V)在2.5和3.5之间; 并且氧化硅和氮化硅之间的V等离子体蚀刻步骤的选择性为至少10。
摘要:
The present invention provides methods of producing substantially void-free trench structures. After deposition of an a-Si or polysilicon layer in a trench formed in a semiconductor, the a-Si or polysilicon is exposed to hydrogen at an elevated temperature.
摘要:
A method of filling high ratio trenches on a substrate is described. First, an oxidizable layer is deposited on the substrate. Thereafter, a trench fill oxide is deposited on the substrate and on the oxidizable layer. Afterwards, the resulting structure is annealed using an oxygen containing gas such that the oxidizable layer is oxidized.
摘要:
The present invention related to doping of amorphous silicon and polysilicon in trench structures for semiconductor devices. A single gas phase doping step is performed after a thin layer of amorphous silicon or polysilicon is deposited in the trench. The gas phase doping occurs at elevated temperature and moderate pressure to yield a dopant concentration on the order of 1×1020 atoms/cm3.
摘要翻译:本发明涉及用于半导体器件的沟槽结构中的非晶硅和多晶硅的掺杂。 在沟槽中沉积薄层非晶硅或多晶硅之后,进行单一气相掺杂步骤。 气相掺杂在升高的温度和中等压力下发生,以产生约1×10 20原子/ cm 3的量级的掺杂剂浓度。
摘要:
The present invention relates to a transistor comprising a gate channel area and a gate stack having mechanical stress arranged on the gate channel area.