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公开(公告)号：US20100161901A9
公开(公告)日：2010-06-24
申请号：US11193634
申请日：2005-08-01
IPC分类号： G06F12/00
CPC分类号： G06F12/0864 , G06F12/1054 , Y02D10/13
摘要： The application describes a data processor operable to process data, and comprising: a cache in which a storage location of a data item within said cache is identified by an address, said cache comprising a plurality of storage locations and said data processor comprising a cache directory operable to store a physical address indicator for each storage location comprising stored data; a hash value generator operable to generate a generated hash value from at least some of said bits of said address said generated hash value having fewer bits than said address; a buffer operable to store a plurality of hash values relating to said plurality of storage locations within said cache; wherein in response to a request to access said data item said data processor is operable to compare said generated hash value with at least some of said plurality of hash values stored within said buffer and in response to a match to indicate a indicated storage location of said data item; and said data processor is operable to access one of said physical address indicators stored within said cache directory corresponding to said indicated storage location and in response to said accessed physical address indicator not indicating said address said data processor is operable to invalidate said indicated storage location within said cache.
摘要翻译： 应用程序描述可操作以处理数据的数据处理器，并且包括：高速缓存，其中通过地址识别所述高速缓存内的数据项的存储位置，所述高速缓存包括多个存储位置，并且所述数据处理器包括高速缓存目录 可操作地存储包括存储的数据的每个存储位置的物理地址指示符; 哈希值发生器，用于从所述地址的所述比特中的至少一些产生生成的散列值，所述哈希值生成的哈希值具有比所述地址少的位; 缓冲器，用于存储与所述高速缓存内的所述多个存储位置相关的多个散列值; 其中响应于访问所述数据项的请求，所述数据处理器可操作以将所生成的散列值与所述缓冲器中存储的所述多个散列值中的至少一些进行比较，并响应于匹配来指示所述数据项的所指示的存储位置 数据项; 并且所述数据处理器可操作以访问存储在与所述指示的存储位置相对应的所述高速缓存目录内的所述物理地址指示符之一，并且响应于所述访问的物理地址指示符不指示所述地址，所述数据处理器可操作以使所述指示的存储位置无效 说缓存。
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公开(公告)号：US20070028051A1
公开(公告)日：2007-02-01
申请号：US11193633
申请日：2005-08-01
IPC分类号： G06F12/00
CPC分类号： G06F12/0864 , G06F12/1054 , G06F2212/1028 , Y02D10/13
摘要： The application discloses a data processor operable to process data, said data processor comprising: a cache having a data item storage location identified by an address; a hash value generator operable to generate a hash value from at least some of said bits of said address said hash value having fewer bits than said address; a buffer operable to store a plurality of hash values relating to a plurality of storage locations within said cache; wherein in response to a request to access said data item storage location said data processor is operable to compare a hash value generated from said address with at least some of said plurality of hash values stored within said buffer. The comparison providing an indication of the storage location of the data item.
摘要翻译： 该应用公开了一种可操作以处理数据的数据处理器，所述数据处理器包括：具有由地址识别的数据项存储位置的高速缓存; 哈希值生成器，用于从所述地址的所述比特中的至少一些产生哈希值，所述哈希值具有比所述地址少的比特; 缓冲器，用于存储与所述高速缓存中的多个存储位置相关的多个散列值; 其中响应于访问所述数据项存储位置的请求，所述数据处理器可操作以将从所述地址生成的散列值与存储在所述缓冲器内的所述多个散列值中的至少一些进行比较。 该比较提供数据项的存储位置的指示。
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公开(公告)号：US20070113058A1
公开(公告)日：2007-05-17
申请号：US11273493
申请日：2005-11-14
IPC分类号： G06F9/44
CPC分类号： G06F9/381 , G06F9/30036 , G06F9/325 , G06F9/3885 , G06F9/3887
摘要： An apparatus comprising detection logic configured to detect a loop among a set of instructions, the loop comprising one or more instructions of a first type of instruction and a second type of instruction and a co-processor configured to execute the loop detected by the detection logic, the co-processor comprising an instruction queue. The apparatus further comprises fetch logic configured to fetch instructions; decode logic configured to determine instruction type; a processor configured to execute the loop detected by the detection logic, wherein the loop comprises one or more instructions of the first type of instruction, and an execution unit configured to execute the loop detected by the detection logic.
摘要翻译： 一种装置，包括被配置为检测一组指令中的循环的检测逻辑，该循环包括第一类型的指令和第二类型的指令的一个或多个指令，以及被配置为执行由检测逻辑检测到的循环的协处理器 协处理器包括指令队列。 所述设备还包括被配置为获取指令的提取逻辑; 解码逻辑配置为确定指令类型; 被配置为执行由检测逻辑检测到的循环的处理器，其中所述循环包括所述第一类型的指令的一个或多个指令，以及被配置为执行由所述检测逻辑检测到的所述循环的执行单元。
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公开(公告)号：US20060271738A1
公开(公告)日：2006-11-30
申请号：US11136169
申请日：2005-05-24
IPC分类号： G06F12/00
CPC分类号： G06F12/0897 , G06F9/30043 , G06F9/3824 , G06F9/3885 , G06F12/0811 , G06F12/0888 , G06F2212/1021
摘要： A processor comprises decode logic that determines an instruction type for each instruction fetched, a first level cache, a second level cache coupled to the first level cache, and control logic operatively coupled to the first and second level caches. The control logic preferably causes cache linefills to be performed to the first level cache upon cache misses for a first type of instruction, but precludes linefills from being performed to the first level cache for a second type of instruction.
摘要翻译： 处理器包括解码逻辑，其确定所取得的每条指令的指令类型，第一级高速缓存，耦合到第一级高速缓存的第二级高速缓存以及可操作地耦合到第一和第二级高速缓存的控制逻辑。 控制逻辑优选地在对于第一类型的指令的高速缓存未命中时，对第一级高速缓存执行高速缓存行填充，但是排除了对于第二类型的指令而对第一级高速缓存执行排线。
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公开(公告)号：US20060200649A1
公开(公告)日：2006-09-07
申请号：US11060142
申请日：2005-02-17
CPC分类号： G06F9/30043 , G06F9/30014 , G06F9/30032 , G06F9/3816
摘要： A method comprising loading a plurality of data bytes from a data cache in response to a load instruction, determining the most significant bit of at least one of the data bytes using a first logic, arranging at least some of the data bytes onto a data bus using a second logic substantially coupled in parallel with the first logic, and performing a sign extension on the data bus using the second logic.
摘要翻译： 一种方法，包括响应于加载指令从数据高速缓冲存储器加载多个数据字节，使用第一逻辑确定至少一个数据字节的最高有效位，将至少一些数据字节排列到数据总线上 使用基本上与第一逻辑并联的第二逻辑，以及使用第二逻辑在数据总线上执行符号扩展。
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公开(公告)号：US20070028047A1
公开(公告)日：2007-02-01
申请号：US11193634
申请日：2005-08-01
IPC分类号： G06F12/00
CPC分类号： G06F12/0864 , G06F12/1054 , Y02D10/13
摘要： The application describes a data processor operable to process data, and comprising: a cache in which a storage location of a data item within said cache is identified by an address, said cache comprising a plurality of storage locations and said data processor comprising a cache directory operable to store a physical address indicator for each storage location comprising stored data; a hash value generator operable to generate a generated hash value from at least some of said bits of said address said generated hash value having fewer bits than said address; a buffer operable to store a plurality of hash values relating to said plurality of storage locations within said cache; wherein in response to a request to access said data item said data processor is operable to compare said generated hash value with at least some of said plurality of hash values stored within said buffer and in response to a match to indicate a indicated storage location of said data item; and said data processor is operable to access one of said physical address indicators stored within said cache directory corresponding to said indicated storage location and in response to said accessed physical address indicator not indicating said address said data processor is operable to invalidate said indicated storage location within said cache.
摘要翻译： 应用程序描述可操作以处理数据的数据处理器，并且包括：高速缓存，其中通过地址识别所述高速缓存内的数据项的存储位置，所述高速缓存包括多个存储位置，并且所述数据处理器包括高速缓存目录 可操作地存储包括存储的数据的每个存储位置的物理地址指示符; 哈希值发生器，用于从所述地址的所述比特中的至少一些产生生成的散列值，所述哈希值生成的哈希值具有比所述地址少的位; 缓冲器，用于存储与所述高速缓存内的所述多个存储位置相关的多个散列值; 其中响应于访问所述数据项的请求，所述数据处理器可操作以将所生成的散列值与所述缓冲器中存储的所述多个散列值中的至少一些进行比较，并响应于匹配来指示所述数据项的所指示的存储位置 数据项; 并且所述数据处理器可操作以访问存储在与所述指示的存储位置相对应的所述高速缓存目录内的所述物理地址指示符之一，并且响应于所述访问的物理地址指示符不指示所述地址，所述数据处理器可操作以使所述指示的存储位置无效 说缓存。
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7.发明申请System and method for high performance, power efficient store buffer forwarding 有权用于高性能，高效能存储缓冲区转发的系统和方法公开(公告)号：US20060047912A1
公开(公告)日：2006-03-02
申请号：US11214501
申请日：2005-08-30
IPC分类号： G06F12/00
CPC分类号： G06F12/0864 , G06F9/3824 , G06F9/3826 , G06F9/3834 , G06F9/3842 , G06F9/3861 , G06F12/0855 , G06F2212/6032 , G06F2212/6082 , Y02D10/13
摘要： The present disclosure describes a system and method for high performance, power efficient store buffer forwarding. Some illustrative embodiments may include a system, comprising: a processor coupled to an address bus; a cache memory that couples to the address bus and comprises cache data (the cache memory divided into a plurality of ways); and a store buffer that couples to the address bus, and comprises store buffer data, a store buffer way and a store buffer index. The processor selects the store buffer data for use by a data load operation if a selected way of the plurality of ways matches the store buffer way, and if at least part of the bus address matches the store buffer index.
摘要翻译： 本公开描述了用于高性能，功率效率的存储缓冲器转发的系统和方法。 一些说明性实施例可以包括系统，包括：耦合到地址总线的处理器; 缓存存储器，其耦合到地址总线并且包括高速缓存数据（被分成多个方式的高速缓冲存储器）; 以及存储缓冲器，其耦合到地址总线，并且包括存储缓冲器数据，存储缓冲器方式和存储缓冲器索引。 如果多个方式的选定方式与存储缓冲器方式相匹配，并且总线地址的至少一部分与存储缓冲器索引匹配，则处理器选择存储缓冲器数据以供数据加载操作使用。
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公开(公告)号：US20060047884A1
公开(公告)日：2006-03-02
申请号：US11109163
申请日：2005-04-19
IPC分类号： G06F12/00
CPC分类号： G06F12/0864 , G06F12/1054 , G06F2212/1028 , Y02D10/13
摘要： A system and method for power efficient memory caching. Some illustrative embodiments may include a system comprising: a hash address generator coupled to an address bus (the hash address generator converts a bus address present on the address bus into a current hashed address); a cache memory coupled to the address bus (the cache memory comprises a tag stored in one of a plurality of tag cache ways and data stored in one of a plurality of data cache ways); and a hash memory coupled to the address bus (the hash memory comprises a saved hashed address, the saved hashed address associated with the data and the tag). Less than all of the plurality of tag cache ways are enabled when the current hashed address matches the saved hashed addresses. An enabled tag cache way comprises the tag.
摘要翻译： 一种用于高效内存缓存的系统和方法。 一些说明性实施例可以包括：系统，其包括：耦合到地址总线的散列地址发生器（所述散列地址生成器将存在于所述地址总线上的总线地址转换为当前散列的地址）; 耦合到所述地址总线的高速缓存存储器（所述高速缓冲存储器包括存储在多个标签高速缓存路径中的一个中的标签和存储在多个数据高速缓存路径之一中的数据）; 以及耦合到地址总线的散列存储器（散列存储器包括保存的散列地址，与数据和标签相关联的保存的散列地址）。 当当前散列的地址与保存的散列地址匹配时，小于所有多个标签高速缓存方式被启用。 启用的标签缓存方式包括标签。
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