公开(公告)号：US20120019273A1

公开(公告)日：2012-01-26

申请号：US13188802

申请日：2011-07-22

申请人： John R. Turner ,  Nathan Charland

发明人： John R. Turner ,  Nathan Charland

IPC分类号： G01R31/3187

CPC分类号： G01R31/2844 ,  G01R31/2884 ,  G01R31/31701

摘要： This application provides apparatus and methods for initiating tests in an interface circuit without using inputs of the interface circuit dedicated to initiating the tests. In an example, a test mode interface circuit can include a voltage comparator configured compare a first voltage to a second voltage, a ripple counter configured to count pulses from a processor when the voltage comparator indicates that the first voltage is greater than the second voltage, and wherein the test mode interface circuit is configured to provide a test mode enable signal and an indication of the a desired test mode an interface circuit that includes the test mode interface circuit.

摘要翻译： 该应用提供用于在接口电路中启动测试而不使用专用于启动测试的接口电路的输入的装置和方法。 在一个示例中，测试模式接口电路可以包括将第一电压与第二电压进行比较的电压比较器，当电压比较器指示第一电压大于第二电压时，纹波计数器被配置为对来自处理器的脉冲进行计数， 并且其中所述测试模式接口电路被配置为提供测试模式使能信号和期望测试模式的指示，所述接口电路包括所述测试模式接口电路。

公开(公告)号：US08829932B2

公开(公告)日：2014-09-09

申请号：US13188802

申请日：2011-07-22

申请人： John R. Turner ,  Nathan Charland

发明人： John R. Turner ,  Nathan Charland

IPC分类号： G01R31/3187 ,  G01R31/28 ,  G01R31/317

CPC分类号： G01R31/2844 ,  G01R31/2884 ,  G01R31/31701

摘要： This application provides apparatus and methods for initiating tests in an interface circuit without using inputs of the interface circuit dedicated to initiating the tests. In an example, a test mode interface circuit can include a voltage comparator configured compare a first voltage to a second voltage, a ripple counter configured to count pulses from a processor when the voltage comparator indicates that the first voltage is greater than the second voltage, and wherein the test mode interface circuit is configured to provide a test mode enable signal and an indication of the a desired test mode an interface circuit that includes the test mode interface circuit.

摘要翻译： 该应用提供用于在接口电路中启动测试而不使用专用于启动测试的接口电路的输入的装置和方法。 在一个示例中，测试模式接口电路可以包括将第一电压与第二电压进行比较的电压比较器，当电压比较器指示第一电压大于第二电压时，纹波计数器被配置为对来自处理器的脉冲进行计数， 并且其中所述测试模式接口电路被配置为提供测试模式使能信号和期望测试模式的指示，所述接口电路包括所述测试模式接口电路。

公开(公告)号：US20050207280A1

公开(公告)日：2005-09-22

申请号：US10802436

申请日：2004-03-16

申请人： Michael Fowler ,  James Boomer ,  Nathan Charland

发明人： Michael Fowler ,  James Boomer ,  Nathan Charland

IPC分类号： H03M9/00 ,  H04L5/14 ,  H04L7/00 ,  H04L7/04 ,  H04L7/06 ,  H04L25/45 ,  H04L25/49 ,  G04B47/00 ,  G06F11/00 ,  H03M13/00

CPC分类号： H04L7/0008 ,  H03M9/00 ,  H04L5/14 ,  H04L7/04 ,  H04L7/06 ,  H04L25/45 ,  H04L2007/045

摘要： A bi-directional serializer/deserializer is disclosed using a single bi-directional data line and a single bi-directional clock line. Gated buffers are controlled to operate either sending or receiving data, and a phase locked loop provides a clock to shift data out from a shift register. A reference clock is supplied to the PLL and the PLL generates a synchronous bit clock. The bit clock is sent over the clock line in parallel with the serial data bits, and the PLL bit clock is synchronized to the data bits. Two data boundary bits are inserted between the word data bits, the boundary data bits are arranged with a logic level transition between the two data boundary bits. Also, at the boundary of the words during the sending of the two boundary data bits, the synchronous bit clock is arranged to have no logic level transition. The receiving system will use the bit clock to serial load the received word and boundary data bits into a shift register. A word boundary is detected by sensing a data bit transition while there is no bit clock.

摘要翻译： 公开了使用单个双向数据线和单个双向时钟线的双向串行器/解串器。 门控缓冲器被控制以发送或接收数据，并且锁相环提供用于从移位寄存器移出数据的时钟。 参考时钟提供给PLL，PLL产生同步位时钟。 位时钟通过时钟线与串行数据位并行发送，PLL位时钟与数据位同步。 在字数据位之间插入两个数据边界位，边界数据位以两个数据边界位之间的逻辑电平转换排列。 而且，在发送两个边界数据位期间的字边界处，同步位时钟被布置成没有逻辑电平转换。 接收系统将使用位时钟将接收的字和边界数据位串行加载到移位寄存器中。 通过在没有位时钟的情况下感测数据位转换来检测字边界。