公开(公告)号：US5504528A

公开(公告)日：1996-04-02

申请号：US379218

申请日：1995-01-27

申请人： Natsuki Koshiro ,  Tatsuya Ishikawa

发明人： Natsuki Koshiro ,  Tatsuya Ishikawa

IPC分类号： H04N5/265 ,  H04N5/44 ,  H04N7/08 ,  H04N7/081 ,  H04N7/26 ,  H04N7/46 ,  H04N21/2365 ,  H04N21/434 ,  H04N7/12

CPC分类号： H04N21/2365 ,  H04N19/59 ,  H04N21/4347 ,  H04N7/0806 ,  H04N19/30

摘要： A video transmission apparatus that has a first input terminal for receiving a low-resolution TV signal. The apparatus also has a second input terminal for receiving a high-resolution TV signal and for outputting said high-resolution TV signal. The apparatus converts the low-resolution TV signal into a signal having a format which is equal to that of the high-resolution TV signal. The apparatus selects either the signal, which has been produced by converting low-resolution TV signal into a signal having a format which is equal to that of the high-resolution TV signal, or the high-resolution TV signal, which is outputted from the second input terminal The signal, which has been produced by converting low-resolution TV signal into a signal having a format which is equal to that of the high-resolution TV signal, is fitted into the high-resolution TV signal. The apparatus encodes the selected signal into a digital high-efficiency coded signal, and outputs a signal indicative thereof. Finally, the apparatus transmits the signal produced by encoding the selected signal.

公开(公告)号：US5768326A

公开(公告)日：1998-06-16

申请号：US631198

申请日：1996-04-12

申请人： Natsuki Koshiro ,  Atsushi Hirota ,  Noriya Sakamoto

发明人： Natsuki Koshiro ,  Atsushi Hirota ,  Noriya Sakamoto

IPC分类号： H04N5/06 ,  H03L7/06 ,  H03L7/08 ,  H03L7/093 ,  H03L7/18 ,  H04B1/26 ,  H04L7/033 ,  H04L27/22 ,  H04N7/56 ,  H03D3/24

CPC分类号： H04N7/56 ,  H03L7/0807 ,  H03L7/093 ,  H03L7/18 ,  H04L7/033

摘要： A PLL circuit for use in a digital broadcasting receiver includes a receiver for receiving a bit stream containing program clock references (PCRs) transmitted from a broadcast station. The PCRs correspond to a frequency and phase of a transmitter system clock. The circuit also contains an oscillator for generating receiver system clocks, a counter responsive to the system clocks, and a connection to allow the bit stream to flow from the receiver to the oscillator. A controller controls the counter based on differences between the PCRs in the bit stream and the counter output. A load control means successively loads the PCRs on the counter in their order of transmission to lock the frequency and phase of the receiver system clock provided from the oscillator with the frequency and phase of the transmitter system clock. This arrangement allows quick adjustment of the receiver system clock frequency and phase by removing the influence of the insertion intervals of the PCRs in the bit stream when making the adjustment.

摘要翻译： 用于数字广播接收机的PLL电路包括用于接收包含从广播台发送的节目时钟参考（PCR）的比特流的接收机。 PCR对应于发射机系统时钟的频率和相位。 该电路还包含用于产生接收机系统时钟的振荡器，响应系统时钟的计数器以及允许比特流从接收机流向振荡器的连接。 控制器根据位流中的PCR和计数器输出之间的差异来控制计数器。 负载控制装置依次按照发送顺序对计数器上的PCR进行加载，以便以发射机系统时钟的频率和相位锁定从振荡器提供的接收机系统时钟的频率和相位。 这种布置允许通过在进行调整时消除位于比特流中的PCR的插入间隔的影响来快速调整接收机系统时钟频率和相位。

公开(公告)号：US06373904B1

公开(公告)日：2002-04-16

申请号：US09119737

申请日：1998-07-21

申请人： Noriya Sakamoto ,  Masahiro Yamada ,  Atsushi Hirota ,  Natsuki Koshiro ,  Eiichiro Tomonaga ,  Tsukasa Kudo

发明人： Noriya Sakamoto ,  Masahiro Yamada ,  Atsushi Hirota ,  Natsuki Koshiro ,  Eiichiro Tomonaga ,  Tsukasa Kudo

IPC分类号： H04N544

CPC分类号： H04H40/18 ,  H04H60/15 ,  H04H60/16 ,  H04N5/4401 ,  H04N5/63 ,  H04N7/163 ,  H04N21/4181 ,  H04N21/42676 ,  H04N21/42692 ,  H04N21/4349 ,  H04N21/4436 ,  H04N21/4623 ,  Y02D70/26

摘要： A digital broadcast receiving device includes a first processor for extracting added information, a storage device for storing the added information, and a second processor having a low power consumption mode and a normal power mode, for effecting the circuit control for the watching and listening operation according to a preset program and the added information. The first processor informs the second processor that the added information is extracted, the second processor changes the mode thereof to the normal power mode when it is informed from the first processor that the added information is extracted while it is set in the low power consumption mode in the standby state, writes the added information extracted by the first processor into the storage device, and changes the mode thereof into the low power consumption mode after completion of the write operation.

摘要翻译： 数字广播接收装置包括用于提取附加信息的第一处理器，用于存储附加信息的存储装置，以及具有低功耗模式和正常功率模式的第二处理器，用于实现用于观看和收听操作的电路控制 根据预设程序和添加的信息。 第一处理器通知第二处理器附加的信息被提取，当第二处理器被设置为低功耗模式时，从第一处理器通知添加的信息被提取时，第二处理器将其模式改变为正常功率模式 在待机状态下，将由第一处理器提取的添加信息写入存储装置，并且在完成写入操作之后将其模式改变为低功耗模式。

公开(公告)号：US5442398A

公开(公告)日：1995-08-15

申请号：US88031

申请日：1993-07-06

申请人： Natsuki Koshiro ,  Tatsuya Ishikawa

发明人： Natsuki Koshiro ,  Tatsuya Ishikawa

IPC分类号： H04N5/265 ,  H04N5/44 ,  H04N7/08 ,  H04N7/081 ,  H04N7/26 ,  H04N7/46 ,  H04N21/2365 ,  H04N21/434 ,  H04N7/12

CPC分类号： H04N21/2365 ,  H04N19/59 ,  H04N21/4347 ,  H04N7/0806 ,  H04N19/30

摘要： A video transmission apparatus that has a first input terminal for receiving a low-resolution TV signal. The apparatus also has a second input terminal for receiving a high-resolution TV signal and for outputting said high-resolution TV signal. The apparatus converts the low-resolution TV signal into a signal having a format which is equal to that of the high-resolution TV signal. The apparatus selects either the signal, which has been produced by converting low-resolution TV signal into a signal having a format which is equal to that of the high-resolution TV signal, or the high-resolution TV signal, which is outputted from the second input terminal The signal, which has been produced by converting low-resolution TV signal into a signal having a format which is equal to that of the high-resolution TV signal, is fitted into the high-resolution TV signal. The apparatus encodes the selected signal into a digital high-efficiency coded signal, and outputs a signal indicative thereof. Finally, the apparatus transmits the signal produced by encoding the selected signal.

摘要翻译： 一种具有用于接收低分辨率TV信号的第一输入端的视频传输装置。 该装置还具有用于接收高分辨率TV信号并输出​​所述高分辨率TV信号的第二输入端。 该装置将低分辨率TV信号转换成具有与高分辨率TV信号相同格式的信号。 该装置选择通过将低分辨率TV信号转换成具有与高分辨率TV信号的格式相同的格式的信号而产生的信号或从该高分辨率TV信号输出的高分辨率TV信号 第二输入端子通过将低分辨率TV信号转换成具有与高分辨率TV信号的格式相等的格式的信号而产生的信号被拟合到高分辨率TV信号中。 该装置将所选择的信号编码为数字高效编码信号，并输出表示其的信号。 最后，设备发送通过对所选信号进行编码而产生的信号。