公开(公告)号：US06930503B2

公开(公告)日：2005-08-16

申请号：US10835945

申请日：2004-04-30

申请人： Joseph C. Sher ,  David D. Siek ,  Huy Thanh Vo ,  Nicholas Van Heel ,  Victor Wong ,  Hua Zheng

发明人： Joseph C. Sher ,  David D. Siek ,  Huy Thanh Vo ,  Nicholas Van Heel ,  Victor Wong ,  Hua Zheng

IPC分类号： G01R31/26 ,  G01R31/30 ,  G11C5/14 ,  G11C29/02 ,  G11C29/12 ,  G01R31/02 ,  G11C29/00

CPC分类号： G11C29/02 ,  G01R31/3004 ,  G11C5/145 ,  G11C5/146 ,  G11C29/021 ,  G11C29/028 ,  G11C29/12 ,  G11C29/12005 ,  G11C2029/5004

摘要： A voltage generating circuit for generating internal voltage for a packaged integrated circuit memory device, is controllable to provide incremental adjustments in the voltage for testing of the memory device. The voltage generating circuit permits internally generated voltages of the memory device, such as the substrate voltage Vbb, the DVC2 voltage, and the pumped voltage Vccp, to be controlled externally through the application of test signals via the conventional test function, in performing standard device tests such as the static refresh test, logic 1s and 0s margin testing, and the like for packaged memory devices. Also, programmable circuits including programmable logic devices, such as anti-fuses, are provided that are programmable to maintain the voltage at a magnitude to which it is adjusted.

摘要翻译： 用于产生用于封装的集成电路存储器件的内部电压的电压产生电路是可控的，以提供用于存储器件测试的电压的增量调节。 电压产生电路允许存储器件的内部产生的电压，例如衬底电压Vbb，DVC2电压和泵浦电压Vccp，通过经由常规测试功能施加测试信号在外部进行控制，以执行标准器件 诸如静态刷新测试，逻辑1s和0s裕量测试之类的测试，等等用于封装的存储器件。 此外，提供了包括可编程逻辑器件（例如抗熔丝）的可编程电路，其可编程以将电压维持在其调节幅度。

公开(公告)号：US06522154B2

公开(公告)日：2003-02-18

申请号：US09811096

申请日：2001-03-16

申请人： John Atkinson Fifield ,  Mark David Jacunski ,  Thomas Martin Maffitt ,  Nicholas Van Heel

发明人： John Atkinson Fifield ,  Mark David Jacunski ,  Thomas Martin Maffitt ,  Nicholas Van Heel

IPC分类号： G01R2726

CPC分类号： G01R31/2648

摘要： A method of, and a circuit for, measuring a capacitor gate dielectric thickness. The method includes the step of providing a circuit including a gate dielectric capacitor, and charging the circuit with a known current. A voltage output from said circuit is measured, and this voltage is proportional to the gate dielectric capacitor thickness. The present invention may be effectively employed to obtain a number of important advantages. First, because the supply voltage scales with gate dielectric thickness, chip performance is maximized, even when gate oxide runs thick. Furthermore, oxide reliability is not affected because a constant electric field is guaranteed.

摘要翻译： 用于测量电容器栅极电介质厚度的方法和电路。 该方法包括提供包括栅介质电容器的电路，并用已知电流对电路充电的步骤。 测量从所述电路输出的电压，并且该电压与栅介质电容器厚度成比例。 本发明可以有效地用于获得许多重要的优点。 首先，由于电源电压随栅极电介质厚度而变化，芯片性能最大化，即使栅氧化层厚。 此外，由于保证了恒定的电场，氧化物可靠性不受影响。

公开(公告)号：US20050052218A1

公开(公告)日：2005-03-10

申请号：US10657362

申请日：2003-09-08

申请人： Michael Killian ,  Nicholas van Heel

发明人： Michael Killian ,  Nicholas van Heel

IPC分类号： G11C7/00 ,  G11C17/18 ,  G11C29/00 ,  H01H37/76

CPC分类号： G11C17/18 ,  G11C29/789

摘要： Information concerning a condition of a fuse is stored in a latch circuit and may be corrected. A first signal is supplied to the latch circuit which sets the latch circuit in a first state when the fuse is in a first condition and keeps the latch circuit unchanged when the fuse is in a second condition. While the first signal is being supplied, a second signal is supplied to the latch circuit that keeps the latch circuit in the first state when the fuse is in the first condition and sets the latch circuit in a second state when the fuse is in the second condition.

摘要翻译： 关于保险丝的状况的信息存储在锁存电路中，并且可以被校正。 第一信号被提供给锁存电路，当锁存器处于第一状态时，将锁存电路设置在第一状态，并且当保险丝处于第二状态时使闩锁电路保持不变。 当提供第一信号时，当熔丝处于第一状态时，将锁存电路保持在第一状态的锁存电路提供第二信号，并且当熔丝处于第二状态时将锁存电路设置在第二状态 条件。

公开(公告)号：US06756805B2

公开(公告)日：2004-06-29

申请号：US10295499

申请日：2002-11-15

申请人： Joseph C. Sher ,  David D. Siek ,  Huy Thanh Vo ,  Nicholas Van Heel ,  Victor Wong ,  Hua Zheng

发明人： Joseph C. Sher ,  David D. Siek ,  Huy Thanh Vo ,  Nicholas Van Heel ,  Victor Wong ,  Hua Zheng

IPC分类号： G01R104

CPC分类号： G11C29/02 ,  G01R31/3004 ,  G11C5/145 ,  G11C5/146 ,  G11C29/021 ,  G11C29/028 ,  G11C29/12 ,  G11C29/12005 ,  G11C2029/5004

摘要： A voltage generating circuit for generating internal voltage for a packaged integrated circuit memory device, is controllable to provide incremental adjustments in the voltage for testing of the memory device. The voltage generating circuit permits internally generated voltages of the memory device, such as the substrate voltage Vbb, the DVC2 voltage, and the pumped voltage Vccp, to be controlled externally through the application of test signals via the conventional test function, in performing standard device tests such as the static refresh test, logic 1s and 0s margin testing, and the like for packaged memory devices. Also, programmable circuits including programmable logic devices, such as anti-fuses, are provided that are programmable to maintain the voltage at a magnitude to which it is adjusted.

公开(公告)号：US20050270058A1

公开(公告)日：2005-12-08

申请号：US11200372

申请日：2005-08-09

申请人： Joseph Sher ,  David Siek ,  Huy Vo ,  Nicholas Van Heel ,  Victor Wong ,  Hua Zheng

发明人： Joseph Sher ,  David Siek ,  Huy Vo ,  Nicholas Van Heel ,  Victor Wong ,  Hua Zheng

IPC分类号： G01R31/26 ,  G01R31/30 ,  G11C5/14 ,  G11C29/02 ,  G11C29/12

CPC分类号： G11C29/02 ,  G01R31/3004 ,  G11C5/145 ,  G11C5/146 ,  G11C29/021 ,  G11C29/028 ,  G11C29/12 ,  G11C29/12005 ,  G11C2029/5004

摘要： A voltage generating circuit for generating internal voltage for a packaged integrated circuit memory device, is controllable to provide incremental adjustments in the voltage for testing of the memory device. The voltage generating circuit permits internally generated voltages of the memory device, such as the substrate voltage Vbb, the DVC2 voltage, and the pumped voltage Vccp, to be controlled externally through the application of test signals via the conventional test function, in performing standard device tests such as the static refresh test, logic 1s and 0s margin testing, and the like for packaged memory devices. Also, programmable circuits including programmable logic devices, such as anti-fuses, are provided that are programmable to maintain the voltage at a magnitude to which it is adjusted.

摘要翻译： 用于产生用于封装的集成电路存储器件的内部电压的电压产生电路是可控的，以提供用于存储器件测试的电压的增量调节。 电压产生电路允许通过常规测试功能在执行标准中通过施加测试信号来外部控制存储器件的内部产生的电压，例如衬底电压Vbb，DVC 2电压和泵浦电压Vccp。 诸如静态刷新测试，逻辑1s和0s边缘测试等设备测试等，用于封装的存储器件。 此外，提供了包括可编程逻辑器件（例如抗熔丝）的可编程电路，其可编程以将电压维持在其调节幅度。

公开(公告)号：US06496027B1

公开(公告)日：2002-12-17

申请号：US08916994

申请日：1997-08-21

申请人： Joseph C. Sher ,  David D. Siek ,  Huy Thanh Vo ,  Nicholas Van Heel ,  Victor Wong ,  Hua Zheng

发明人： Joseph C. Sher ,  David D. Siek ,  Huy Thanh Vo ,  Nicholas Van Heel ,  Victor Wong ,  Hua Zheng

IPC分类号： G01R3102

CPC分类号： G11C29/02 ,  G01R31/3004 ,  G11C5/145 ,  G11C5/146 ,  G11C29/021 ,  G11C29/028 ,  G11C29/12 ,  G11C29/12005 ,  G11C2029/5004

摘要： A voltage generating circuit for generating internal voltage for a packaged integrated circuit memory device, is controllable to provide incremental adjustments in the voltage for testing of the memory device. The voltage generating circuit permits internally generated voltages of the memory device, such as the substrate voltage Vbb, the DVC2 voltage, and the pumped voltage Vccp, to be controlled externally through the application of test signals via the conventional test function, in performing standard device tests such as the static refresh test, logic 1s and 0s margin testing, and the like for packaged memory devices. Also, programmable circuits including programmable logic devices, such as anti-fuses, are provided that are programmable to maintain the voltage at a magnitude to which it is adjusted.

摘要翻译： 用于产生用于封装的集成电路存储器件的内部电压的电压产生电路是可控的，以提供用于存储器件测试的电压的增量调节。 电压产生电路允许存储器件的内部产生的电压，例如衬底电压Vbb，DVC2电压和泵浦电压Vccp，通过经由常规测试功能施加测试信号在外部进行控制，以执行标准器件 诸如静态刷新测试，逻辑1s和0s裕量测试之类的测试，等等用于封装的存储器件。 此外，提供了包括可编程逻辑器件（例如抗熔丝）的可编程电路，其可编程以将电压维持在其调节幅度。