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    System for testing integrated circuit devices
    1.
    发明授权
    System for testing integrated circuit devices 有权
    集成电路设备测试系统

    公开(公告)号：US06930503B2

    公开(公告)日：2005-08-16

    申请号：US10835945

    申请日：2004-04-30

    申请人： Joseph C. Sher ,  David D. Siek ,  Huy Thanh Vo ,  Nicholas Van Heel ,  Victor Wong ,  Hua Zheng

    发明人： Joseph C. Sher ,  David D. Siek ,  Huy Thanh Vo ,  Nicholas Van Heel ,  Victor Wong ,  Hua Zheng

    IPC分类号： G01R31/26 ,  G01R31/30 ,  G11C5/14 ,  G11C29/02 ,  G11C29/12 ,  G01R31/02 ,  G11C29/00

    CPC分类号： G11C29/02 ,  G01R31/3004 ,  G11C5/145 ,  G11C5/146 ,  G11C29/021 ,  G11C29/028 ,  G11C29/12 ,  G11C29/12005 ,  G11C2029/5004

    摘要： A voltage generating circuit for generating internal voltage for a packaged integrated circuit memory device, is controllable to provide incremental adjustments in the voltage for testing of the memory device. The voltage generating circuit permits internally generated voltages of the memory device, such as the substrate voltage Vbb, the DVC2 voltage, and the pumped voltage Vccp, to be controlled externally through the application of test signals via the conventional test function, in performing standard device tests such as the static refresh test, logic 1s and 0s margin testing, and the like for packaged memory devices. Also, programmable circuits including programmable logic devices, such as anti-fuses, are provided that are programmable to maintain the voltage at a magnitude to which it is adjusted.

    摘要翻译： 用于产生用于封装的集成电路存储器件的内部电压的电压产生电路是可控的，以提供用于存储器件测试的电压的增量调节。 电压产生电路允许存储器件的内部产生的电压，例如衬底电压Vbb，DVC2电压和泵浦电压Vccp，通过经由常规测试功能施加测试信号在外部进行控制，以执行标准器件 诸如静态刷新测试，逻辑1s和0s裕量测试之类的测试，等等用于封装的存储器件。 此外，提供了包括可编程逻辑器件（例如抗熔丝）的可编程电路，其可编程以将电压维持在其调节幅度。

    System for testing integrated circuit devices
    3.
    发明授权
    System for testing integrated circuit devices 失效
    集成电路设备测试系统

    公开(公告)号：US06496027B1

    公开(公告)日：2002-12-17

    申请号：US08916994

    申请日：1997-08-21

    申请人： Joseph C. Sher ,  David D. Siek ,  Huy Thanh Vo ,  Nicholas Van Heel ,  Victor Wong ,  Hua Zheng

    发明人： Joseph C. Sher ,  David D. Siek ,  Huy Thanh Vo ,  Nicholas Van Heel ,  Victor Wong ,  Hua Zheng

    IPC分类号： G01R3102

    CPC分类号： G11C29/02 ,  G01R31/3004 ,  G11C5/145 ,  G11C5/146 ,  G11C29/021 ,  G11C29/028 ,  G11C29/12 ,  G11C29/12005 ,  G11C2029/5004

    摘要： A voltage generating circuit for generating internal voltage for a packaged integrated circuit memory device, is controllable to provide incremental adjustments in the voltage for testing of the memory device. The voltage generating circuit permits internally generated voltages of the memory device, such as the substrate voltage Vbb, the DVC2 voltage, and the pumped voltage Vccp, to be controlled externally through the application of test signals via the conventional test function, in performing standard device tests such as the static refresh test, logic 1s and 0s margin testing, and the like for packaged memory devices. Also, programmable circuits including programmable logic devices, such as anti-fuses, are provided that are programmable to maintain the voltage at a magnitude to which it is adjusted.

    摘要翻译： 用于产生用于封装的集成电路存储器件的内部电压的电压产生电路是可控的，以提供用于存储器件测试的电压的增量调节。 电压产生电路允许存储器件的内部产生的电压，例如衬底电压Vbb，DVC2电压和泵浦电压Vccp，通过经由常规测试功能施加测试信号在外部进行控制，以执行标准器件 诸如静态刷新测试，逻辑1s和0s裕量测试之类的测试，等等用于封装的存储器件。 此外，提供了包括可编程逻辑器件（例如抗熔丝）的可编程电路，其可编程以将电压维持在其调节幅度。

    System for testing integrated circuit devices
    4.
    发明申请
    System for testing integrated circuit devices 审中-公开
    集成电路设备测试系统

    公开(公告)号：US20050270058A1

    公开(公告)日：2005-12-08

    申请号：US11200372

    申请日：2005-08-09

    申请人： Joseph Sher ,  David Siek ,  Huy Vo ,  Nicholas Van Heel ,  Victor Wong ,  Hua Zheng

    发明人： Joseph Sher ,  David Siek ,  Huy Vo ,  Nicholas Van Heel ,  Victor Wong ,  Hua Zheng

    IPC分类号： G01R31/26 ,  G01R31/30 ,  G11C5/14 ,  G11C29/02 ,  G11C29/12

    CPC分类号： G11C29/02 ,  G01R31/3004 ,  G11C5/145 ,  G11C5/146 ,  G11C29/021 ,  G11C29/028 ,  G11C29/12 ,  G11C29/12005 ,  G11C2029/5004

    摘要： A voltage generating circuit for generating internal voltage for a packaged integrated circuit memory device, is controllable to provide incremental adjustments in the voltage for testing of the memory device. The voltage generating circuit permits internally generated voltages of the memory device, such as the substrate voltage Vbb, the DVC2 voltage, and the pumped voltage Vccp, to be controlled externally through the application of test signals via the conventional test function, in performing standard device tests such as the static refresh test, logic 1s and 0s margin testing, and the like for packaged memory devices. Also, programmable circuits including programmable logic devices, such as anti-fuses, are provided that are programmable to maintain the voltage at a magnitude to which it is adjusted.

    摘要翻译： 用于产生用于封装的集成电路存储器件的内部电压的电压产生电路是可控的，以提供用于存储器件测试的电压的增量调节。 电压产生电路允许通过常规测试功能在执行标准中通过施加测试信号来外部控制存储器件的内部产生的电压，例如衬底电压Vbb，DVC 2电压和泵浦电压Vccp。 诸如静态刷新测试，逻辑1s和0s边缘测试等设备测试等，用于封装的存储器件。 此外，提供了包括可编程逻辑器件（例如抗熔丝）的可编程电路，其可编程以将电压维持在其调节幅度。

    Dislplay panel, flat-panel display device and driving method thereof
    5.
    发明授权
    Dislplay panel, flat-panel display device and driving method thereof 有权
    显示面板，平板显示装置及其驱动方法

    公开(公告)号：US08896640B2

    公开(公告)日：2014-11-25

    申请号：US13578622

    申请日：2012-06-13

    申请人： Hua Zheng ,  Cheng-hung Chen

    发明人： Hua Zheng ,  Cheng-hung Chen

    IPC分类号： G09G5/10

    CPC分类号： G09G5/10 ,  G09G3/20 ,  G09G3/2092 ,  G09G2300/0408 ,  G09G2310/0281 ,  G09G2320/0223

    摘要： The display panel includes data driven chip and at least two scanning driven chips. The second scanning signal input terminal of each of the scanning driven chip is connected to a first scanning signal output terminal of the data driven chip by corresponding transmission circuits. At least one transmission circuit includes a serially connected resistor so that sum of impedance of the transmission circuits are equal, or the difference of the impedance of the transmission circuit is less than a predetermined value. In addition, a flat-panel display device with uniform brightness and a driving method thereof are also provided.

    摘要翻译： 显示面板包括数据驱动芯片和至少两个扫描驱动芯片。 每个扫描驱动芯片的第二扫描信号输入端通过相应的传输电路连接到数据驱动芯片的第一扫描信号输出端。 至少一个传输电路包括串联的电阻器，使得发送电路的阻抗之和相等，或者发送电路的阻抗差小于预定值。 此外，还提供了具有均匀亮度的平板显示装置及其驱动方法。

    Layer based scalable multimedia datastream compression
    7.
    发明申请
    Layer based scalable multimedia datastream compression 审中-公开
    基于层的可扩展多媒体数据流压缩

    公开(公告)号：US20080294446A1

    公开(公告)日：2008-11-27

    申请号：US11805245

    申请日：2007-05-22

    申请人： Linfeng Guo ,  Hua Zheng ,  Mark Sydorenko ,  Yang Li

    发明人： Linfeng Guo ,  Hua Zheng ,  Mark Sydorenko ,  Yang Li

    IPC分类号： G10L19/00

    CPC分类号： G10L19/167 ,  G10L19/0017 ,  G10L19/0204 ,  G10L19/24

    摘要： Source signals, such as audio and/or video data, are encoded into multiple, consecutive frequency bands. These bands are referred to as coding layers. Rather than performing complex bit-slice operations, a disclosed technique enables an agile and simplified response to transmission channel throughput variations. Specifically, if it becomes necessary to restrict the rate of data transmission to avoid receiver buffer underflow resulting from transmission channel degradation, layers from the transmitted signal are omitted, beginning with the highest frequency bands. Efficient and agile bit rate scalability during data streaming through wired or wireless networks and during local playback is thus enabled.

    摘要翻译： 诸如音频和/或视频数据的源信号被编码成多个连续的频带。 这些频带被称为编码层。 所公开的技术不是执行复杂的位片操作，而是能够对传输信道吞吐量变化进行敏捷和简化的响应。 具体地，如果需要限制数据传输速率以避免由于传输信道恶化导致的接收机缓冲器下溢，则从最高频带开始，从发送信号中省去层。 因此，通过有线或无线网络和本地播放期间的数据流传输期间，高效且敏捷的比特率可扩展性得以实现。

    Synchronous dynamic random access memory device
    9.
    发明授权
    Synchronous dynamic random access memory device 有权

    公开(公告)号：US06512711B1

    公开(公告)日：2003-01-28

    申请号：US09572820

    申请日：2000-05-16

    申请人： Jeffrey P. Wright ,  Hua Zheng

    发明人： Jeffrey P. Wright ,  Hua Zheng

    IPC分类号： G11C700

    CPC分类号： G11C7/1084 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/109

    摘要： A synchronous semiconductor memory device has improved layout and circuitry so as to provide rapid operation. Data paths between sub-arrays and memory cells and corresponding DQ pads are equalized to provide approximately equal line delays, transmission losses, etc. Input clock circuitry converts a “asynchronous” external clock signal and external clock enable signal to an internal “synchronous” clock signal. Input command signals are not stored in input registers, but instead are latched so as to provide such input signals rapidly downstream. Multiple redundant compare circuitry is provided to improve delays inherent in selecting between external or internal addresses. Input/output pull up circuitry is enabled during both read and write operations, but shortened during write operations. Two or more voltage pump circuits are employed that permit sharing of power therebetween to compensate for increased power demands to row lines, data output lines, etc.