公开(公告)号：US20090129176A1

公开(公告)日：2009-05-21

申请号：US12332458

申请日：2008-12-11

申请人： Huy Vo ,  Charles Ingalls

发明人： Huy Vo ,  Charles Ingalls

IPC分类号： G11C11/416 ,  G11C7/00 ,  G11C8/00

CPC分类号： G11C7/1069 ,  G11C7/1012 ,  G11C7/1039 ,  G11C7/1042 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1096 ,  G11C11/4096 ,  G11C2207/002

摘要： A memory device comprising a memory array having a plurality of memory cells, and a plurality of peripheral devices for reading data out of and writing data into the memory array, the peripheral devices include a first write driver connected to a first input/output line, the first input/output line being associated with a digitline connected to certain of the plurality of memory cells, a first read amplifier connected to the first input/output line, a first input/output device responsive to a first column select signal for connecting the first input/output line to the digitline, a second write driver connected to a second input/output line, the second input/output line being associated with the digitline, a second read amplifier connected to the second input/output line, and a second input/output device responsive to a second column select signal for connecting the second input/output line to the digitline.

摘要翻译： 一种存储器件，包括具有多个存储器单元的存储器阵列和用于将数据读出并将数据写入存储器阵列的多个外围器件，所述外围器件包括连接到第一输入/输出线的第一写入驱动器， 所述第一输入/输出线与连接到所述多个存储器单元中的某些的数字线相关联，连接到所述第一输入/输出线的第一读取放大器，响应于第一列选择信号的第一输入/输出装置， 与数字线的第一输入/输出线，连接到第二输入/输出线的第二写入驱动器，与数字线相关联的第二输入/输出线，连接到第二输入/输出线的第二读取放大器， 输入/输出装置响应于用于将第二输入/输出线连接到数字线的第二列选择信号。

公开(公告)号：US20080225624A1

公开(公告)日：2008-09-18

申请号：US12072125

申请日：2008-02-22

申请人： Huy Vo ,  Charles Ingalls

发明人： Huy Vo ,  Charles Ingalls

IPC分类号： G11C8/00

CPC分类号： G11C7/1069 ,  G11C7/1012 ,  G11C7/1039 ,  G11C7/1042 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1096 ,  G11C11/4096 ,  G11C2207/002

摘要： A memory device comprising a memory array having a plurality of memory cells, and a plurality of peripheral devices for reading data out of and writing data into the memory array, the peripheral devices include a first write driver connected to a first input/output line, the first input/output line being associated with a digitline connected to certain of the plurality of memory cells, a first read amplifier connected to the first input/output line, a first input/output device responsive to a first column select signal for connecting the first input/output line to the digitline, a second write driver connected to a second input/output line, the second input/output line being associated with the digitline, a second read amplifier connected to the second input/output line, and a second input/output device responsive to a second column select signal for connecting the second input/output line to the digitline.

摘要翻译： 一种存储器件，包括具有多个存储器单元的存储器阵列和用于将数据读出并将数据写入存储器阵列的多个外围器件，所述外围器件包括连接到第一输入/输出线的第一写入驱动器， 所述第一输入/输出线与连接到所述多个存储器单元中的某些的数字线相关联，连接到所述第一输入/输出线的第一读取放大器，响应于第一列选择信号的第一输入/输出装置， 与数字线的第一输入/输出线，连接到第二输入/输出线的第二写入驱动器，与数字线相关联的第二输入/输出线，连接到第二输入/输出线的第二读取放大器， 输入/输出装置响应于用于将第二输入/输出线连接到数字线的第二列选择信号。

公开(公告)号：US07203124B2

公开(公告)日：2007-04-10

申请号：US10860881

申请日：2004-06-03

申请人： Tae Hyoung Kim ,  Huy Vo ,  Greg Blodgett

发明人： Tae Hyoung Kim ,  Huy Vo ,  Greg Blodgett

IPC分类号： G11C8/00

CPC分类号： G11C8/08

摘要： A negative word line driver employs devices to maintain the potential difference between the active word line signal and the inactive word line signal while reducing the need for a significant negative voltage supply. One form of the negative word line driver employs an isolation element to couple the word line to ground when the inputs to the word line driver indicate the word line should not be active, while the word line is also coupled to the negative voltage supply. Another form of the form of the negative word line driver receives as inputs the voltages to be driven on the word line and can be implemented with fewer transistors but still allows the word line to be driven at a negative voltage with a reduced negative voltage supply.

摘要翻译： 负字线驱动器使用器件来维持有源字线信号和非活动字线信号之间的电位差，同时减少对显着的负电压电源的需要。 当字线驱动器的输入指示字线不应该被激活，同时字线也耦合到负电压源时，一种形式的负字线驱动器采用隔离元件将字线耦合到地。 负字形线驱动器的形式的另一种形式作为输入端接收要在字线上驱动的电压，并且可以用较少的晶体管来实现，但是仍然允许字线在负电压下以负电压供给被驱动。

公开(公告)号：US06809986B2

公开(公告)日：2004-10-26

申请号：US10232953

申请日：2002-08-29

申请人： Tae Hyoung Kim ,  Huy Vo ,  Greg Blodgett

发明人： Tae Hyoung Kim ,  Huy Vo ,  Greg Blodgett

IPC分类号： G11C800

CPC分类号： G11C8/08

摘要： A negative word line driver employs devices to maintain the potential difference between the active word line signal and the inactive word line signal while reducing the need for a significant negative voltage supply. One form of the negative word line driver employs an isolation element to couple the word line to ground when the inputs to the word line driver indicate the word line should not be active, while the word line is also coupled to the negative voltage supply. Another form of the form of the negative word line driver receives as inputs the voltages to be driven on the word line and can be implemented with fewer transistors but still allows the word line to be driven at a negative voltage with a reduced negative voltage supply.

摘要翻译： 负字线驱动器使用器件来维持有源字线信号和非活动字线信号之间的电位差，同时减少对显着的负电压电源的需要。 当字线驱动器的输入指示字线不应该被激活，同时字线也耦合到负电压源时，一种形式的负字线驱动器采用隔离元件将字线耦合到地。 负字形线驱动器的形式的另一种形式作为输入端接收要在字线上驱动的电压，并且可以用较少的晶体管来实现，但是仍然允许字线在负电压下以负电压供给被驱动。

公开(公告)号：US08913447B2

公开(公告)日：2014-12-16

申请号：US13168723

申请日：2011-06-24

申请人： Jacob Robert Anderson ,  Kang-Yong Kim ,  Tadashi Yamamoto ,  Zer Liang ,  Huy Vo

发明人： Jacob Robert Anderson ,  Kang-Yong Kim ,  Tadashi Yamamoto ,  Zer Liang ,  Huy Vo

IPC分类号： G11C7/00

CPC分类号： G11C8/12 ,  G06F13/4234 ,  G11C7/00 ,  G11C7/10 ,  Y02D10/14 ,  Y02D10/151

摘要： Memories containing command decoder, chip enable, and signal truncation circuits are disclosed. One such command decoder circuit may include command decoder logic configured to receive command signals and output a decoded command to an interconnect bus responsive to a chip select signal having an active state. Decoder circuits may also prevent coupling commands to the interconnect bus based on the receipt of chip select signals having inactive states. The memory further may include chip enable circuits having control logic configured to receive chip select signals and provide the chip select signals to an interconnect bus responsive to receiving a valid command. Chip enable circuits may also prevent coupling chip select signals to the interconnect bus from chip enable signals based on the receipt of invalid command signals. Signal truncation circuits may be used to shorten and/or shift chip select signals to increase timing margins and improve the reliability of command execution by memories.

摘要翻译： 公开了包含命令解码器，芯片使能和信号截断电路的存储器。 一个这样的命令解码器电路可以包括命令解码器逻辑，其被配置为接收命令信号，并且响应于具有活动状态的片选信号而将解码的命令输出到互连总线。 解码器电路还可以基于接收到具有无效状态的片选信号来防止到互连总线的耦合命令。 存储器还可以包括具有控制逻辑的芯片使能电路，其配置成接收芯片选择信号并且响应于接收到有效命令而将芯片选择信号提供给互连总线。 芯片使能电路还可以基于无效命令信号的接收，防止从芯片使能信号将互连芯片选择信号耦合到互连总线。 信号截断电路可用于缩短和/或移位芯片选择信号以增加定时裕度并提高存储器执行命令的可靠性。

公开(公告)号：US08499187B2

公开(公告)日：2013-07-30

申请号：US13209234

申请日：2011-08-12

申请人： Kang-Yong Kim ,  Jacob Robert Anderson ,  Huy Vo

发明人： Kang-Yong Kim ,  Jacob Robert Anderson ,  Huy Vo

IPC分类号： G06F1/14

CPC分类号： G11C7/20 ,  G11C29/003 ,  G11C29/32 ,  G11C29/50012 ,  G11C2029/0407 ,  H01L25/0657

摘要： Apparatuses, master-slave detect circuits, memories, and methods are disclosed. One such method includes performing a master detect phase during which a memory unit in a memory group is determined to be a master memory unit, determining at each memory unit its location relative to other memory units, and determining at each memory unit its location in the memory group based on a total number of slave memory units and its location relative to other memory units.

摘要翻译： 公开了设备，主 - 从检测电路，存储器和方法。 一种这样的方法包括执行主检测阶段，在此期间，将存储器组中的存储器单元确定为主存储器单元，在每个存储器单元处确定其相对于其他存储器单元的位置，以及在每个存储器单元处确定其位于 存储器组基于从属存储器单元的总数及其相对于其他存储器单元的位置。

公开(公告)号：US20110069560A1

公开(公告)日：2011-03-24

申请号：US12565655

申请日：2009-09-23

申请人： HUY VO

发明人： HUY VO

IPC分类号： G11C7/10 ,  G11C7/00 ,  G11C8/18

CPC分类号： G11C7/1027 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1084 ,  G11C11/406 ,  G11C11/4082 ,  G11C11/4093

摘要： Embodiments of a data capture system and method may be used in a variety of devices, such as in memory controllers and memory devices. The data capture system and method may generate a first set of periodic signals and a second set of periodic signals that differs from the first set. Either the first set of periodic signals or the second set of periodic signals may be selected and used to generate a set of data capture signals. The selection of either the first set or the second set may be made on the basis of the number of serial data digits in a previously captured burst of data. The data capture signals may then be used to capture a burst of serial data digits.

摘要翻译： 数据采集​​系统和方法的实施例可以用在各种设备中，例如在存储器控制器和存储设备中。 数据采集​​系统和方法可以产生与第一组不同的第一组周期信号和第二组周期性信号。 可以选择第一组周期信号或第二组周期信号来生成一组数据捕获信号。 可以基于先前捕获的数据突发中的串行数据数字的数量来进行第一组或第二组的选择。 然后可以使用数据捕获信号来捕获串行数据数字的突发。

公开(公告)号：US20080027782A1

公开(公告)日：2008-01-31

申请号：US11697922

申请日：2007-04-09

申请人： Juliana Freire ,  Claudio Silva ,  Louis Bavoil ,  Steven Callahan ,  Emanuele Santos ,  Carlos Scheidegger ,  Huy Vo

发明人： Juliana Freire ,  Claudio Silva ,  Louis Bavoil ,  Steven Callahan ,  Emanuele Santos ,  Carlos Scheidegger ,  Huy Vo

IPC分类号： G06F9/46

CPC分类号： G06Q10/06316 ,  G06F9/451 ,  G06Q10/06

摘要： A method of and a system for presenting a plurality of workflows that describe an evolutionary workflow process associated with creating a result are provided. A first workflow is received at a first device. The first workflow comprises a first module which applies a first instruction to form a first result. A modification of the first workflow is received at the first device. The received modification includes a second workflow which includes a second module that applies a second instruction to form a second result. The evolutionary workflow process is presented to a user at a second device. The evolutionary workflow process includes the first workflow and the second workflow and indicates a parent-child relationship between the first workflow and the second workflow.

摘要翻译： 提供了一种用于呈现描述与创建结果相关联的进化工作流程的多个工作流的方法和系统。 在第一设备处接收到第一工作流程。 第一工作流程包括应用第一指令以形成第一结果的第一模块。 在第一设备处接收到第一工作流程的修改。 所接收的修改包括第二工作流程，其包括应用第二指令以形成第二结果的第二模块。 将进化工作流程呈现给第二设备的用户。 进化工作流程包括第一工作流程和第二工作流程，并指示第一工作流程和第二工作流程之间的父子关系。

公开(公告)号：US20120327728A1

公开(公告)日：2012-12-27

申请号：US13168723

申请日：2011-06-24

申请人： Jacob Robert Anderson ,  Kang-Yong Kim ,  Tadashi Yamamoto ,  Zer Liang ,  Huy Vo

发明人： Jacob Robert Anderson ,  Kang-Yong Kim ,  Tadashi Yamamoto ,  Zer Liang ,  Huy Vo

IPC分类号： G11C7/00

CPC分类号： G11C8/12 ,  G06F13/4234 ,  G11C7/00 ,  G11C7/10 ,  Y02D10/14 ,  Y02D10/151

摘要： Memories containing command decoder, chip enable, and signal truncation circuits are disclosed. One such command decoder circuit may include command decoder logic configured to receive command signals and output a decoded command to an interconnect bus responsive to a chip select signal having an active state. Decoder circuits may also prevent coupling commands to the interconnect bus based on the receipt of chip select signals having inactive states. The memory further may include chip enable circuits having control logic configured to receive chip select signals and provide the chip select signals to an interconnect bus responsive to receiving a valid command. Chip enable circuits may also prevent coupling chip select signals to the interconnect bus from chip enable signals based on the receipt of invalid command signals. Signal truncation circuits may be used to shorten and/or shift chip select signals to increase timing margins and improve the reliability of command execution by memories.

摘要翻译： 公开了包含命令解码器，芯片使能和信号截断电路的存储器。 一个这样的命令解码器电路可以包括命令解码器逻辑，其被配置为接收命令信号，并且响应于具有活动状态的片选信号而将解码的命令输出到互连总线。 解码器电路还可以基于接收到具有无效状态的片选信号来防止到互连总线的耦合命令。 存储器还可以包括具有控制逻辑的芯片使能电路，其配置成接收芯片选择信号并且响应于接收到有效命令而将芯片选择信号提供给互连总线。 芯片使能电路还可以基于无效命令信号的接收，防止从芯片使能信号将互连芯片选择信号耦合到互连总线。 信号截断电路可用于缩短和/或移位芯片选择信号以增加定时裕度并提高存储器执行命令的可靠性。

公开(公告)号：US20120188828A1

公开(公告)日：2012-07-26

申请号：US13438634

申请日：2012-04-03

申请人： Huy Vo

发明人： Huy Vo

IPC分类号： G11C7/10 ,  G11C7/00

CPC分类号： G11C7/1027 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1084 ,  G11C11/406 ,  G11C11/4082 ,  G11C11/4093

摘要： Embodiments of a data capture system and method may be used in a variety of devices, such as in memory controllers and memory devices. The data capture system and method may generate a first set of periodic signals and a second set of periodic signals that differs from the first set. Either the first set of periodic signals or the second set of periodic signals may be selected and used to generate a set of data capture signals. The selection of either the first set or the second set may be made on the basis of the number of serial data digits in a previously captured burst of data. The data capture signals may then be used to capture a burst of serial data digits.

摘要翻译： 数据采集​​系统和方法的实施例可以用在各种设备中，例如在存储器控制器和存储设备中。 数据采集​​系统和方法可以产生与第一组不同的第一组周期信号和第二组周期性信号。 可以选择第一组周期信号或第二组周期信号来生成一组数据捕获信号。 可以基于先前捕获的数据突发中的串行数据数字的数量来进行第一组或第二组的选择。 然后可以使用数据捕获信号来捕获串行数据数字的突发。