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    Performance driven multi-valued variable supply voltage scheme for low power design of VLSI circuits and systems
    2.
    发明授权
    Performance driven multi-valued variable supply voltage scheme for low power design of VLSI circuits and systems 有权
    性能驱动的多值可变电源电压方案，用于VLSI电路和系统的低功耗设计

    公开(公告)号：US06225858B1

    公开(公告)日：2001-05-01

    申请号：US09473897

    申请日：1999-12-28

    申请人： Carlo Guardiani ,  Roberta Burger Riccio ,  Roberto Zafalon ,  Andrea Veggetti ,  Nicola Dragone

    发明人： Carlo Guardiani ,  Roberta Burger Riccio ,  Roberto Zafalon ,  Andrea Veggetti ,  Nicola Dragone

    IPC分类号： G05F110

    CPC分类号： G06F17/505

    摘要： A method of reducing power consumption of an electric circuit having a primary supply voltage and first and second circuit blocks is discussed. The method includes determining for the first circuit block an operation time for a first critical path of the first circuit block and determining for the second circuit block an operation time of a second critical path of the second circuit block. From those operation times, the method determines that the operation time of the first critical path is faster than the operation time of the second critical path. The method then creates a first supply voltage for the first circuit block that is less than the primary supply voltage in response to determining that the operation time of the first critical path is faster than the operation time of the second critical path.

    摘要翻译： 讨论了降低具有初级电源电压的电路的功耗的方法以及第一和第二电路块。 该方法包括为第一电路块确定第一电路块的第一关键路径的操作时间，并确定第二电路块的第二电路块的第二关键路径的操作时间。 从这些操作时间，该方法确定第一关键路径的操作时间比第二关键路径的操作时间快。 响应于确定第一关键路径的操作时间比第二关键路径的操作时间快，该方法为第一电路块产生小于主电源电压的第一电源电压。

    Integrated circuit design to optimize manufacturability
    3.
    发明申请
    Integrated circuit design to optimize manufacturability 审中-公开
    集成电路设计，优化可制造性

    公开(公告)号：US20060253810A1

    公开(公告)日：2006-11-09

    申请号：US10572151

    申请日：2003-09-16

    申请人： Carlo Guardiani ,  Nicola Dragone ,  John Kibarian ,  Enrico Malavasi ,  Rijko Radocic ,  Andrzej Strojwas

    发明人： Carlo Guardiani ,  Nicola Dragone ,  John Kibarian ,  Enrico Malavasi ,  Rijko Radocic ,  Andrzej Strojwas

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5068 ,  G06F17/5081

    摘要： Library design elements (102) are analyzed for manufacturability to be used in designing an IC chip to be manufactured using a particular manufacturing process. The library design elements from a library are obtained. Manufacturability attributes (104) of the library design elements are determined for the particular manufacturing process, where manufacturability attributes include yield-related attributes. Library views (106) with manufacturability attributes for the library design elements are then generated, which are utilizing by an electronic design automation (EDA) tool.

    摘要翻译： 分析库设计元素（102），以便制造可用于设计使用特定制造工艺制造的IC芯片。 获取图书馆的图书馆设计元素。 确定库设计元素的可制造性属性（104），用于特定制造过程，其中可制造性属性包括屈服相关属性。 然后生成具有库设计元素的可制造性属性的库视图（106），其由电子设计自动化（EDA）工具利用。