公开(公告)号：US07487474B2

公开(公告)日：2009-02-03

申请号：US10541076

申请日：2003-11-17

申请人： Dennis Ciplickas ,  Joe Davis ,  Christopher Hess ,  Sherry Lee ,  Enrico Malavasi ,  Abdulmobeen Mohammad ,  Ratibor Radojcic ,  Brian Stine ,  Rakesh Vallishayee ,  Stefano Zanella ,  Nicola Dragone ,  Carlo Guardiani ,  Michel Quarantelli ,  Stefano Tonello ,  Joshi Aniruddha

发明人： Dennis Ciplickas ,  Joe Davis ,  Christopher Hess ,  Sherry Lee ,  Enrico Malavasi ,  Abdulmobeen Mohammad ,  Ratibor Radojcic ,  Brian Stine ,  Rakesh Vallishayee ,  Stefano Zanella ,  Nicola Dragone ,  Carlo Guardiani ,  Michel Quarantelli ,  Stefano Tonello ,  Joshi Aniruddha

IPC分类号： G06F17/50

CPC分类号： G06F17/5045

摘要： An integrated circuit is designed to improve yield when manufacturing the integrated circuit, by obtaining a design element from a set of design elements used in designing integrated circuits. A variant design element is created based on the obtained design element, where a feature of the obtained design element is modified to create the variant design element. A yield to area ratio for the variant design element is determined. If the yield to area ratio of the variant design element is greater than a yield to area ratio of the obtained design element, the variant design element is retained to be used in designing the integrated circuit.

摘要翻译： 集成电路设计用于通过从设计集成电路中使用的一组设计元素获得设计元素来提高制造集成电路时的产量。 基于获得的设计元素创建变体设计元素，其中修改所获得的设计元素的特征以创建变体设计元素。 确定变体设计元素的产出与面积比。 如果变形设计元素的产率与面积之比大于所获得的设计元素的面积比，则变形设计元素被保留以用于设计集成电路。

公开(公告)号：US07807480B2

公开(公告)日：2010-10-05

申请号：US12002094

申请日：2007-12-14

申请人： Brian Stine ,  Victor Kitch ,  Mark Zwald ,  Stefano Tonello

发明人： Brian Stine ,  Victor Kitch ,  Mark Zwald ,  Stefano Tonello

IPC分类号： H01L21/66

CPC分类号： G11C29/025 ,  G01R31/2884 ,  G11C17/14 ,  G11C29/006 ,  G11C29/24 ,  G11C2029/0403 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： A test cell for localizing defects includes a first active region, a second active region formed substantially parallel to the first active region, a third active region formed substantially parallel to the first and second active regions, a fourth active region formed between the first and second active regions, and a fifth active region formed between the second and third active regions. The fourth and fifth active regions are formed adjacent to opposite end portions of the second active region. The fourth and fifth active regions are also formed substantially perpendicular to the second active region.

摘要翻译： 用于定位缺陷的测试单元包括第一有源区，基本上平行于第一有源区形成的第二有源区，基本上平行于第一和第二有源区形成的第三有源区，形成在第一和第二有源区之间的第四有源区 有源区和形成在第二和第三有源区之间的第五有源区。 第四和第五有源区域邻近第二有源区域的相对端部分形成。 第四和第五有源区也基本上垂直于第二有源区形成。

公开(公告)号：US20070118242A1

公开(公告)日：2007-05-24

申请号：US11503433

申请日：2006-08-10

申请人： Brian Stine ,  Christopher Hess ,  John Kibarian ,  Kimon Michaels ,  Joseph Davis ,  Purnendu Mozumder ,  Sherry Lee ,  Larg Weiland ,  Dennis Ciplickas ,  David Stashower

发明人： Brian Stine ,  Christopher Hess ,  John Kibarian ,  Kimon Michaels ,  Joseph Davis ,  Purnendu Mozumder ,  Sherry Lee ,  Larg Weiland ,  Dennis Ciplickas ,  David Stashower

IPC分类号： G06F19/00

CPC分类号： G06F17/5081 ,  G05B15/02 ,  H01L22/20 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： A system and method for predicting yield of integrated circuits includes at least one type of characterization vehicle which incorporates at least one feature which is representative of at least one type of feature to be incorporated in the final integrated circuit product. The characterization vehicle is subjected to at least one of the process operations making up the fabrication cycle to be used in fabricating the integrated circuit product in order to produce a yield model. The yield model embodies a layout as defined by the characterization vehicle and preferably includes features which facilitate the gathering of electrical test data and testing of prototype sections at operating speeds. An extraction engine extracts predetermined layout attributes from a proposed product layout. Operating on the yield model, the extraction engine produces yield predictions as a function of layout attributes and broken down by layers or steps in the fabrication process. These yield predictions are then used to determine which areas in the fabrication process require the most improvement.

摘要翻译： 用于预测集成电路的产量的系统和方法包括至少一种表征车辆，其包括至少一个特征，其代表要并入到最终集成电路产品中的至少一种类型的特征。 表征车辆经受构成制造周期的工艺操作中的至少一个，以用于制造集成电路产品以产生屈服模型。 产量模型体现了由表征车辆定义的布局，并且优选地包括便于在运行速度下收集电测试数据和测试原型部分的特征。 提取引擎从提出的产品布局中提取预定的布局属性。 在产量模型上运行，提取引擎作为布局属性的函数产生产量预测，并在制造过程中按层或步骤细分。 然后使用这些产量预测来确定制造过程中哪些领域需要最大的改进。

公开(公告)号：US20050158888A1

公开(公告)日：2005-07-21

申请号：US11078630

申请日：2005-03-10

申请人： Brian Stine ,  Christopher Hess ,  John Kibarian ,  Kimon Michaels ,  Joseph Davis ,  Purnendu Mozumder ,  Sherry Lee ,  Larg Weiland ,  Dennis Ciplickas ,  David Stashower

发明人： Brian Stine ,  Christopher Hess ,  John Kibarian ,  Kimon Michaels ,  Joseph Davis ,  Purnendu Mozumder ,  Sherry Lee ,  Larg Weiland ,  Dennis Ciplickas ,  David Stashower

IPC分类号： H01L21/00 ,  G01R31/26 ,  G05B15/02 ,  H01L21/02 ,  H01L21/66 ,  H01L23/544

CPC分类号： G06F17/5081 ,  G05B15/02 ,  H01L22/20 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： A system and method for predicting yield of integrated circuits includes at least one type of characterization vehicle which incorporates at least one feature which is representative of at least one type of feature to be incorporated in the final integrated circuit product. The characterization vehicle is subjected to at least one of the process operations making up the fabrication cycle to be used in fabricating the integrated circuit product in order to produce a yield model. The yield model embodies a layout as defined by the characterization vehicle and preferably includes features which facilitate the gathering of electrical test data and testing of prototype sections at operating speeds. An extraction engine extracts predetermined layout attributes from a proposed product layout. Operating on the yield model, the extraction engine produces yield predictions as a function of layout attributes and broken down by layers or steps in the fabrication process. These yield predictions are then used to determine which areas in the fabrication process require the most improvement.

摘要翻译： 用于预测集成电路的产量的系统和方法包括至少一种表征车辆，其包括至少一个特征，其代表要并入到最终集成电路产品中的至少一种类型的特征。 表征车辆经受构成制造周期的工艺操作中的至少一个，以用于制造集成电路产品以产生屈服模型。 产量模型体现了由表征车辆定义的布局，并且优选地包括便于在运行速度下收集电测试数据和测试原型部分的特征。 提取引擎从提出的产品布局中提取预定的布局属性。 在产量模型上运行，提取引擎作为布局属性的函数产生产量预测，并在制造过程中按层或步骤细分。 然后使用这些产量预测来确定制造过程中哪些领域需要最大的改进。

公开(公告)号：US20050122123A1

公开(公告)日：2005-06-09

申请号：US10508506

申请日：2003-03-26

申请人： Brian Stine ,  Christopher Hess ,  Larg Weiland ,  Deniis Ciplickas

发明人： Brian Stine ,  Christopher Hess ,  Larg Weiland ,  Deniis Ciplickas

IPC分类号： H01L23/544 ,  G01R31/26

CPC分类号： H01L22/34

摘要： A test vehicle (100) comprises a substrate (99), a plurality of nested serpentine lines (202) on the substrate, and a plurality of test pads (204) on the substrate. Each serpentine line has a plurality of turn sections that comprise two parallel line segments connected by a perpendicular line segment. Each of the plurality of test pads is connected to a respective turn section of a respective one of the nested serpentine lines. Each pair of test pads connected to one of the subset of the nested serpentine lines has at least a respectively different turn section portion connected therebetween.

摘要翻译： 测试车辆（100）包括衬底（99），在衬底上的多个嵌套蛇形线（202）和在衬底上的多个测试焊盘（204）。 每个蛇形线具有多个转弯部分，其包括通过垂直线段连接的两条平行线段。 多个测试垫中的每一个连接到相应的一个嵌套蛇形线的相应转向部分。 连接到嵌套蛇形线的子集中的一个的每对测试焊盘至少具有连接在它们之间的分别不同的转向部分。

公开(公告)号：US20060101355A1

公开(公告)日：2006-05-11

申请号：US10541076

申请日：2003-11-17

申请人： Dennis Ciplickas ,  Joe Davis ,  Christopher Hess ,  Sherry Lee ,  Enrico Malavasi ,  Abdulmobeen Mohammad ,  Ratibor Radojcic ,  Brian Stine ,  Rakesh Vallishayee ,  Stefano Zanella ,  Nicola Dragone ,  Carlo Guardiani ,  Michel Quarantelli ,  Stefano Tonello ,  Joshi Aniruddha

发明人： Dennis Ciplickas ,  Joe Davis ,  Christopher Hess ,  Sherry Lee ,  Enrico Malavasi ,  Abdulmobeen Mohammad ,  Ratibor Radojcic ,  Brian Stine ,  Rakesh Vallishayee ,  Stefano Zanella ,  Nicola Dragone ,  Carlo Guardiani ,  Michel Quarantelli ,  Stefano Tonello ,  Joshi Aniruddha

IPC分类号： G06F17/50

CPC分类号： G06F17/5045

摘要： An integrated circuit is designed to improve yield when manufacturing the integrated circuit, by obtaining a design element from a set of design elements used in designing integrated circuits. A variant design element is created based on the obtained design element, where a feature of the obtained design element is modified to create the variant design element. A yield to area ratio for the variant design element is determined. If the yield to area ratio of the variant design element is greater than a yield to area ratio of the obtained design element, the variant design element is retained to be used in designing the integrated circuit

摘要翻译： 集成电路设计用于通过从设计集成电路中使用的一组设计元素获得设计元素来提高制造集成电路时的产量。 基于获得的设计元素创建变体设计元素，其中修改所获得的设计元素的特征以创建变体设计元素。 确定变体设计元素的产出与面积比。 如果变形设计元件的屈服面积比大于获得的设计元素的屈服面积比，则变形设计元素被保留用于设计集成电路

公开(公告)号：US20080169466A1

公开(公告)日：2008-07-17

申请号：US12002094

申请日：2007-12-14

申请人： Brian Stine ,  Victor Kitch ,  Mark Zwald ,  Stefano Tonello

发明人： Brian Stine ,  Victor Kitch ,  Mark Zwald ,  Stefano Tonello

IPC分类号： H01L21/66 ,  H01L23/58 ,  H01L21/50

CPC分类号： G11C29/025 ,  G01R31/2884 ,  G11C17/14 ,  G11C29/006 ,  G11C29/24 ,  G11C2029/0403 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： A test cell for localizing defects includes a first active region, a second active region formed substantially parallel to the first active region, a third active region formed substantially parallel to the first and second active regions, a fourth active region formed between the first and second active regions, and a fifth active region formed between the second and third active regions. The fourth and fifth active regions are formed adjacent to opposite end portions of the second active region. The fourth and fifth active regions are also formed substantially perpendicular to the second active region.

摘要翻译： 用于定位缺陷的测试单元包括第一有源区，基本上平行于第一有源区形成的第二有源区，基本上平行于第一和第二有源区形成的第三有源区，形成在第一和第二有源区之间的第四有源区 有源区和形成在第二和第三有源区之间的第五有源区。 第四和第五有源区域邻近第二有源区域的相对端部分形成。 第四和第五有源区也基本上垂直于第二有源区形成。

公开(公告)号：US20060277506A1

公开(公告)日：2006-12-07

申请号：US11503323

申请日：2006-08-10

申请人： Brian Stine ,  Christopher Hess ,  John Kibarian ,  Kimon Michaels ,  Joseph Davis ,  Purnendu Mozumder ,  Sherry Lee ,  Larg Weiland ,  Dennis Ciplickas ,  David Stashower

发明人： Brian Stine ,  Christopher Hess ,  John Kibarian ,  Kimon Michaels ,  Joseph Davis ,  Purnendu Mozumder ,  Sherry Lee ,  Larg Weiland ,  Dennis Ciplickas ,  David Stashower

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G05B15/02 ,  H01L22/20 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： A system and method for predicting yield of integrated circuits includes at least one type of characterization vehicle which incorporates at least one feature which is representative of at least one type of feature to be incorporated in the final integrated circuit product. The characterization vehicle is subjected to at least one of the process operations making up the fabrication cycle to be used in fabricating the integrated circuit product in order to produce a yield model. The yield model embodies a layout as defined by the characterization vehicle and preferably includes features which facilitate the gathering of electrical test data and testing of prototype sections at operating speeds. An extraction engine extracts predetermined layout attributes from a proposed product layout. Operating on the yield model, the extraction engine produces yield predictions as a function of layout attributes and broken down by layers or steps in the fabrication process. These yield predictions are then used to determine which areas in the fabrication process require the most improvement.

公开(公告)号：US20050074908A1

公开(公告)日：2005-04-07

申请号：US10492513

申请日：2004-10-08

申请人： Dennis Ciplickas ,  Brian Stine ,  Yanwen Fei

发明人： Dennis Ciplickas ,  Brian Stine ,  Yanwen Fei

IPC分类号： H01L23/544 ,  H01L21/66 ,  H01L21/44 ,  H01L23/58 ,  H01L29/10

CPC分类号： H01L22/34

摘要： A test structure comprising a test pattern is formed on a substrate. The test pattern includes a first comb structure having a plurality of tines, and a second structure. The second structure may be a snake structure having a plurality of side walls or a second comb structure having a plurality of side walls. The tines of the first comb structure are positioned within side walls of the snake structure or second comb structure. The tines of the first comb structure are offset from a center of the side walls. Test data collected from the test structure are analyzed, to estimate product yield. The test structure may have a lower layer pattern, such that topographical variations of the lower layer pattern propagate to an upper layer pattern of the test structure.