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    Test cells for semiconductor yield improvement
    3.
    发明授权
    Test cells for semiconductor yield improvement 有权
    测试电池用于半导体产量提高

    公开(公告)号：US07807480B2

    公开(公告)日：2010-10-05

    申请号：US12002094

    申请日：2007-12-14

    申请人： Brian Stine ,  Victor Kitch ,  Mark Zwald ,  Stefano Tonello

    发明人： Brian Stine ,  Victor Kitch ,  Mark Zwald ,  Stefano Tonello

    IPC分类号： H01L21/66

    CPC分类号： G11C29/025 ,  G01R31/2884 ,  G11C17/14 ,  G11C29/006 ,  G11C29/24 ,  G11C2029/0403 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A test cell for localizing defects includes a first active region, a second active region formed substantially parallel to the first active region, a third active region formed substantially parallel to the first and second active regions, a fourth active region formed between the first and second active regions, and a fifth active region formed between the second and third active regions. The fourth and fifth active regions are formed adjacent to opposite end portions of the second active region. The fourth and fifth active regions are also formed substantially perpendicular to the second active region.

    摘要翻译： 用于定位缺陷的测试单元包括第一有源区，基本上平行于第一有源区形成的第二有源区，基本上平行于第一和第二有源区形成的第三有源区，形成在第一和第二有源区之间的第四有源区 有源区和形成在第二和第三有源区之间的第五有源区。 第四和第五有源区域邻近第二有源区域的相对端部分形成。 第四和第五有源区也基本上垂直于第二有源区形成。

    Test Cells for semiconductor yield improvement
    4.
    发明申请
    Test Cells for semiconductor yield improvement 有权
    测试电池用于半导体产量提高

    公开(公告)号：US20080169466A1

    公开(公告)日：2008-07-17

    申请号：US12002094

    申请日：2007-12-14

    申请人： Brian Stine ,  Victor Kitch ,  Mark Zwald ,  Stefano Tonello

    发明人： Brian Stine ,  Victor Kitch ,  Mark Zwald ,  Stefano Tonello

    IPC分类号： H01L21/66 ,  H01L23/58 ,  H01L21/50

    CPC分类号： G11C29/025 ,  G01R31/2884 ,  G11C17/14 ,  G11C29/006 ,  G11C29/24 ,  G11C2029/0403 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A test cell for localizing defects includes a first active region, a second active region formed substantially parallel to the first active region, a third active region formed substantially parallel to the first and second active regions, a fourth active region formed between the first and second active regions, and a fifth active region formed between the second and third active regions. The fourth and fifth active regions are formed adjacent to opposite end portions of the second active region. The fourth and fifth active regions are also formed substantially perpendicular to the second active region.

    摘要翻译： 用于定位缺陷的测试单元包括第一有源区，基本上平行于第一有源区形成的第二有源区，基本上平行于第一和第二有源区形成的第三有源区，形成在第一和第二有源区之间的第四有源区 有源区和形成在第二和第三有源区之间的第五有源区。 第四和第五有源区域邻近第二有源区域的相对端部分形成。 第四和第五有源区也基本上垂直于第二有源区形成。

    Layout for DUT arrays used in semiconductor wafer testing
    5.
    发明申请
    Layout for DUT arrays used in semiconductor wafer testing 失效
    用于半导体晶圆测试的DUT阵列布局

    公开(公告)号：US20070075718A1

    公开(公告)日：2007-04-05

    申请号：US11243016

    申请日：2005-10-03

    申请人： Christopher Hess ,  Angelo Rossoni ,  Stefano Tonello ,  Michele Squicciarini ,  Michele Quarantelli

    发明人： Christopher Hess ,  Angelo Rossoni ,  Stefano Tonello ,  Michele Squicciarini ,  Michele Quarantelli

    IPC分类号： G01R31/26

    CPC分类号： H01L22/34 ,  G01R31/2884 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A layout for devices under test formed on a semiconductor wafer for use in wafer testing includes a first array of devices under test and a first pad set formed adjacent to the first array. The first pad set includes a gate force pad, a source pad, and a drain pad. Each of the devices under test in the first array is connected to the gate pad of the first pad set. Each of the devices under test in the first array is connected to the source pad of the first pad set. Each of the devices under test in the first array is connected to the drain pad of the first pad set.

    摘要翻译： 在用于晶片测试的半导体晶片上形成的被测器件的布局包括被测试器件的第一阵列和与第一阵列相邻形成的第一焊盘组。 第一焊盘组包括栅极力焊盘，源极焊盘和漏极焊盘。 第一阵列中被测试的每个器件连接到第一焊盘组的栅极焊盘。 第一阵列中被测试的每个设备连接到第一焊盘组的源焊盘。 第一阵列中被测试的每个器件连接到第一焊盘组的漏极焊盘。

    LAYOUT FOR DUT ARRAYS USED IN SEMICONDUCTOR WAFER TESTING
    6.
    发明申请
    LAYOUT FOR DUT ARRAYS USED IN SEMICONDUCTOR WAFER TESTING 审中-公开
    在半导体波形测试中使用的DUT阵列的布局

    公开(公告)号：US20090140762A1

    公开(公告)日：2009-06-04

    申请号：US12368603

    申请日：2009-02-10

    申请人： Christopher Hess ,  Angelo Rossoni ,  Stefano Tonello ,  Michele Squicciarini ,  Michele Quarantelli

    发明人： Christopher Hess ,  Angelo Rossoni ,  Stefano Tonello ,  Michele Squicciarini ,  Michele Quarantelli

    IPC分类号： G01R31/26

    CPC分类号： H01L22/34 ,  G01R31/2884 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A layout for devices under test formed on a semiconductor wafer for use in wafer testing includes a first array of devices under test and a first pad set formed adjacent to the first array. The first pad set includes a gate force pad, a source pad, and a drain pad. Each of the devices under test in the first array is connected to the gate pad of the first pad set. Each of the devices under test in the first array is connected to the source pad of the first pad set. Each of the devices under test in the first array is connected to the drain pad of the first pad set.

    摘要翻译： 在用于晶片测试的半导体晶片上形成的被测器件的布局包括被测试器件的第一阵列和与第一阵列相邻形成的第一焊盘组。 第一焊盘组包括栅极力焊盘，源极焊盘和漏极焊盘。 第一阵列中被测试的每个器件连接到第一焊盘组的栅极焊盘。 第一阵列中被测试的每个设备连接到第一焊盘组的源焊盘。 第一阵列中被测试的每个器件连接到第一焊盘组的漏极焊盘。

    Layout for DUT arrays used in semiconductor wafer testing
    7.
    发明授权
    Layout for DUT arrays used in semiconductor wafer testing 失效
    用于半导体晶圆测试的DUT阵列布局

    公开(公告)号：US07489151B2

    公开(公告)日：2009-02-10

    申请号：US11243016

    申请日：2005-10-03

    申请人： Christopher Hess ,  Angelo Rossoni ,  Stefano Tonello ,  Michele Squicciarini ,  Michele Quarantelli

    发明人： Christopher Hess ,  Angelo Rossoni ,  Stefano Tonello ,  Michele Squicciarini ,  Michele Quarantelli

    IPC分类号： G01R31/02 ,  G01R31/26

    CPC分类号： H01L22/34 ,  G01R31/2884 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A layout for devices under test formed on a semiconductor wafer for use in wafer testing includes a first array of devices under test and a first pad set formed adjacent to the first array. The first pad set includes a gate force pad, a source pad, and a drain pad. Each of the devices under test in the first array is connected to the gate pad of the first pad set. Each of the devices under test in the first array is connected to the source pad of the first pad set. Each of the devices under test in the first array is connected to the drain pad of the first pad set.

    摘要翻译： 在用于晶片测试的半导体晶片上形成的被测器件的布局包括被测试器件的第一阵列和与第一阵列相邻形成的第一焊盘组。 第一焊盘组包括栅极力焊盘，源极焊盘和漏极焊盘。 第一阵列中被测试的每个器件连接到第一焊盘组的栅极焊盘。 第一阵列中被测试的每个设备连接到第一焊盘组的源焊盘。 第一阵列中被测试的每个器件连接到第一焊盘组的漏极焊盘。

    Low power RAM memory cell using a precharge line pulse during write operation
    8.
    发明授权
    Low power RAM memory cell using a precharge line pulse during write operation 有权
    在写操作期间使用预充电线脉冲的低功率RAM存储单元

    公开(公告)号：US06380592B2

    公开(公告)日：2002-04-30

    申请号：US09200079

    申请日：1998-11-25

    申请人： Michael Tooher ,  Stefano Tonello

    发明人： Michael Tooher ,  Stefano Tonello

    IPC分类号： H01L2976

    CPC分类号： G11C11/412 ,  Y10S257/903

    摘要： A semiconductor memory cell that includes a word line, two bit lines, a precharge line, and two cross-coupled inverters. Each of the inverters is formed by a P-channel transistor and an N-channel transistor. Additionally, a first access transistor selectively couples one bit line to the output of one inverter, and a second access transistor selectively couples the other bit line to the output of the other inverter. One terminal of the N-channel transistor of each of the inverters is connected to the precharge line. In a preferred embodiment, the access transistors are P-channel transistors and the gate terminal of each PMOS access transistor is connected to the word line. Additionally, the present invention provides a method of writing data to a semiconductor memory cell that is connected to a pair of bit lines.

    摘要翻译： 一种半导体存储单元，包括字线，两位线，预充电线和两个交叉耦合的反相器。 每个反相器由P沟道晶体管和N沟道晶体管形成。 此外，第一存取晶体管选择性地将一个位线耦合到一个反相器的输出，而第二存取晶体管选择性地将另一个位线耦合到另一个反相器的输出端。 每个逆变器的N沟道晶体管的一个端子连接到预充电线。 在优选实施例中，存取晶体管是P沟道晶体管，并且每个PMOS存取晶体管的栅极端子连接到字线。 另外，本发明提供了将数据写入连接到一对位线的半导体存储单元的方法。