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公开(公告)号：US07951679B2
公开(公告)日：2011-05-31
申请号：US11187958
申请日：2005-07-25
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L27/11568
摘要： First, on a semiconductor region of a first conductivity type, a trapping film is formed which stores information by accumulating charges. Then, the trapping film is formed with a plurality of openings, and impurity ions of a second conductivity type are implanted into the semiconductor region from the formed openings, thereby forming a plurality of diffused layers of the second conductivity type in portions of the semiconductor region located below the openings, respectively. An insulating film is formed to cover edges of the trapping film located toward the openings, and then the semiconductor region is subjected to a thermal process in an atmosphere containing oxygen to oxidize upper portions of the diffused layers. Thereby, insulating oxide films are formed in the upper portions of the diffused layers, respectively. Subsequently, a conductive film is formed over the trapping film including the edges thereof to form an electrode.
摘要翻译： 首先，在第一导电类型的半导体区域上，形成通过累积电荷来存储信息的捕获膜。 然后，捕获膜形成有多个开口，并且第二导电类型的杂质离子从形成的开口注入到半导体区域中，从而在半导体区域的部分中形成多个第二导电类型的扩散层 分别位于开口下方。 形成绝缘膜以覆盖位于开口的捕获膜的边缘，然后在含氧气氛中对半导体区域进行热处理，以氧化扩散层的上部。 因此，绝缘氧化膜分别形成在扩散层的上部。 随后，在包括其边缘的捕获膜上形成导电膜以形成电极。
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公开(公告)号：US20110084277A1
公开(公告)日：2011-04-14
申请号：US12973292
申请日：2010-12-20
IPC分类号： H01L27/108
CPC分类号： H01L21/76837 , H01L27/11521 , H01L27/11568 , H01L29/40114 , H01L29/40117
摘要： A semiconductor memory device has a plurality of word line provided on a semiconductor region, extending in a row direction, a plurality of bit lines provided in the semiconductor region, extending in a column direction, and a plurality of memory elements provided at intersections between the plurality of word lines and the plurality of bit lines. Each word line provides a first gate electrode in the corresponding memory element. A lower portion of a side surface of each word line in a direction parallel to an extending direction of the word line is perpendicular to a main surface of the semiconductor region. An upper portion of the side surface is inclined so that a width thereof becomes smaller toward a top thereof.
摘要翻译： 半导体存储器件具有设置在沿行方向延伸的半导体区域上的多个字线，设置在半导体区域中的列列方向上延伸的多个位线，以及设置在列方向上的交叉点处的多个存储元件 多个字线和多个位线。 每个字线在对应的存储元件中提供第一栅电极。 每个字线的与字线的延伸方向平行的方向的侧面的下部垂直于半导体区域的主表面。 侧面的上部倾斜，使得其宽度朝向其顶部变小。
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公开(公告)号：US20100213987A1
公开(公告)日：2010-08-26
申请号：US12632335
申请日：2009-12-07
IPC分类号： H03K17/687 , H01L29/78
CPC分类号： H01L27/105 , H01L27/0207 , H01L27/0266 , H01L27/11519 , H01L27/11526 , H01L27/11565 , H01L27/11573
摘要： A semiconductor device includes an element to be protected formed on a semiconductor substrate, a first protection transistor, and a second protection transistor. The first protection transistor is formed on a first well of a first conductivity type formed in an upper portion of a deep well of a second conductivity type. The second protection transistor is formed on a second well of the second conductivity type. A second source/drain diffusion layer is electrically connected with a third source/drain diffusion layer and at the same potential as the first well. A fourth source/drain diffusion layer is electrically connected with a second diffusion layer and at the same potential as the second well and the second diffusion layer.
摘要翻译： 半导体器件包括形成在半导体衬底上的待保护元件，第一保护晶体管和第二保护晶体管。 第一保护晶体管形成在形成在第二导电类型的深阱的上部中的第一导电类型的第一阱上。 第二保护晶体管形成在第二导电类型的第二阱上。 第二源极/漏极扩散层与第三源极/漏极扩散层电连接并且具有与第一阱相同的电位。 第四源极/漏极扩散层与第二扩散层电连接，并且与第二阱和第二扩散层具有相同的电位。
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公开(公告)号：US07781291B2
公开(公告)日：2010-08-24
申请号：US12551848
申请日：2009-09-01
IPC分类号： H01L21/336
CPC分类号： H01L27/11568 , H01L21/823878 , H01L27/105 , H01L27/1052 , H01L27/11573 , H01L29/792 , Y10S438/954
摘要： A semiconductor device includes a memory section formed at a semiconductor substrate and including a first transistor having an ONO film that can store charges between the semiconductor substrate and a memory electrode and a first STI region for isolating the first transistor, and a CMOS section formed at the semiconductor substrate and including a second transistor having a CMOS electrode and a gate dielectric and a second STI region for isolating the second transistor. The height of the top surface of the first STI region is set equal to or smaller than the height of the top surface of the second STI region.
摘要翻译： 一种半导体器件包括形成在半导体衬底上的存储器部分，并且包括具有可存储半导体衬底和存储电极之间的电荷的ONO膜的第一晶体管和用于隔离第一晶体管的第一STI区域和形成在 半导体衬底并且包括具有CMOS电极和栅极电介质的第二晶体管和用于隔离第二晶体管的第二STI区域。 第一STI区域的顶表面的高度被设定为等于或小于第二STI区域的顶表面的高度。
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公开(公告)号：US20090189214A1
公开(公告)日：2009-07-30
申请号：US12360488
申请日：2009-01-27
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L27/11568
摘要： The semiconductor device includes: a plurality of bit lines formed in stripes in a semiconductor substrate of a first conductivity type, each of the bit lines being a diffusion layer of an impurity of a second conductivity type; a plurality of gate insulation films s formed on regions of the semiconductor substrate between the bit lines; a plurality of word lines formed on the semiconductor substrate via the gate insulating films, the word lines extending in a direction intersecting with the bit lines; and a plurality of bit line isolation diffusion layers formed in regions of the semiconductor substrate between the word lines, each of the bit line isolation diffusion layers being a diffusion layer of an impurity of the first conductivity type. The bit line isolation diffusion layer includes a diffusion suppressor for suppressing diffusion of an impurity.
摘要翻译： 半导体器件包括：在第一导电类型的半导体衬底中以条纹形成的多个位线，每个位线是第二导电类型的杂质的扩散层; 在所述位线之间形成在所述半导体衬底的区域上的多个栅绝缘膜; 经由所述栅极绝缘膜形成在所述半导体衬底上的多个字线，所述字线在与所述位线相交的方向上延伸; 以及在所述字线之间的所述半导体衬底的区域中形成的多个位线隔离扩散层，所述位线隔离扩散层中的每一个为所述第一导电类型的杂质的扩散层。 位线隔离扩散层包括用于抑制杂质扩散的扩散抑制器。
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公开(公告)号：US07439577B2
公开(公告)日：2008-10-21
申请号：US11495780
申请日：2006-07-31
申请人： Takahiko Hashidzume , Nobuyoshi Takahashi , Koji Yoshida , Keita Takahashi , Kiyoshi Kurihara , Yoshiya Moriyama
发明人： Takahiko Hashidzume , Nobuyoshi Takahashi , Koji Yoshida , Keita Takahashi , Kiyoshi Kurihara , Yoshiya Moriyama
IPC分类号： H01L29/792
CPC分类号： H01L27/115 , H01L27/11568
摘要： A semiconductor memory is provided with memory cells including bit lines made of a diffusion layer formed in a semiconductor substrate, charge-trapping gate insulating films formed between the bit lines and word lines formed on the gate insulating films. An interlayer insulating film is formed over the memory cells and bit line contact plugs are formed in the interlayer insulating film to be connected to the bit lines. Further, a light blocking film is formed on at least part of the interlayer insulating film covering the memory cells and part of the light blocking film formed on the interlayer insulating film extends from the surface to the inside of the interlayer insulating film in the neighborhood of the bit line contact plugs.
摘要翻译： 半导体存储器设置有存储单元，存储单元包括由在半导体衬底中形成的扩散层构成的位线，形成在位线和形成在栅极绝缘膜上的字线之间的电荷俘获栅极绝缘膜。 在存储单元之上形成层间绝缘膜，并且在层间绝缘膜中形成位线接触插塞以连接到位线。 此外，在覆盖存储单元的层间绝缘膜的至少一部分上形成遮光膜，并且形成在层间绝缘膜上的遮光膜的一部分从层间绝缘膜的表面延伸到附近的层间绝缘膜的内部 位线接触插头。
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公开(公告)号：US20070108509A1
公开(公告)日：2007-05-17
申请号：US11495780
申请日：2006-07-31
申请人： Takahiko Hashidzume , Nobuyoshi Takahashi , Koji Yoshida , Keita Takahashi , Kiyoshi Kurihara , Yoshiya Moriyama
发明人： Takahiko Hashidzume , Nobuyoshi Takahashi , Koji Yoshida , Keita Takahashi , Kiyoshi Kurihara , Yoshiya Moriyama
IPC分类号： H01L29/792
CPC分类号： H01L27/115 , H01L27/11568
摘要： A semiconductor memory is provided with memory cells including bit lines made of a diffusion layer formed in a semiconductor substrate, charge-trapping gate insulating films formed between the bit lines and word lines formed on the gate insulating films. An interlayer insulating film is formed over the memory cells and bit line contact plugs are formed in the interlayer insulating film to be connected to the bit lines. Further, a light blocking film is formed on at least part of the interlayer insulating film covering the memory cells and part of the light blocking film formed on the interlayer insulating film extends from the surface to the inside of the interlayer insulating film in the neighborhood of the bit line contact plugs.
摘要翻译： 半导体存储器设置有存储单元，存储单元包括由在半导体衬底中形成的扩散层构成的位线，形成在位线和形成在栅极绝缘膜上的字线之间的电荷俘获栅极绝缘膜。 在存储单元之上形成层间绝缘膜，并且在层间绝缘膜中形成位线接触插塞以连接到位线。 此外，在覆盖存储单元的层间绝缘膜的至少一部分上形成遮光膜，并且形成在层间绝缘膜上的遮光膜的一部分从层间绝缘膜的表面延伸到附近的层间绝缘膜的内部 位线接触插头。
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公开(公告)号：US20060022243A1
公开(公告)日：2006-02-02
申请号：US11151542
申请日：2005-06-14
IPC分类号： H01L29/94
CPC分类号： H01L27/115 , H01L27/11519 , H01L27/11568
摘要： A semiconductor memory device has a memory region which is formed on a semiconductor substrate and in which a plurality of memory cells each including a memory transistor are arranged as a matrix using a plurality of impurity diffusion layers (bit lines) and a plurality of gate electrodes (word lines) intersecting each other. The gate electrode of each of the memory transistors has an upper surface thereof formed into a protruding portion which is higher in level at the middle portion than at the edge portions. A silicide layer is formed on the upper surface of the protruding portion of the gate electrode of each of the memory transistors.
摘要翻译： 半导体存储器件具有形成在半导体衬底上的存储区域，其中使用多个杂质扩散层（位线）和多个栅电极将包括存储晶体管的多个存储单元布置为矩阵 （字线）相交。 每个存储晶体管的栅极电极的上表面形成为在中间部分高于边缘部分的高度的突出部分。 在每个存储晶体管的栅电极的突出部分的上表面上形成硅化物层。
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公开(公告)号：US4747627A
公开(公告)日：1988-05-31
申请号：US913280
申请日：1986-09-30
IPC分类号： B61C15/10
CPC分类号： B61C15/102
摘要： A sanding apparatus improves adhesion between a railcar wheel and a rail by supplying adhesion intensifying particles to the contact faces. Sand and/or quartz particles, having diameters such that at least 50% of the particles are 100 to 300 micrometers, are mixed with compressed air and jetted at high velocity through a U-shaped storage chamber, out a nozzle, to the wheel-rail contact area. In the nozzle, a compressed air supply pipe surrounds and projects beyond the end of the particle supply pipe to create an air curtain surrounding the jetted particles. A heater, a heat insulation member, or constantly leaking air may be used to prevent freezing in the pipes.
摘要翻译： 打磨装置通过向接触面提供粘附增强颗粒来提高轨道车轮与轨道之间的粘合性。 具有使至少50％的颗粒为100至300微米的直径的砂和/或石英颗粒与压缩空气混合并通过U形储存室高速喷射出喷嘴， 铁路接触区域。 在喷嘴中，压缩空气供应管围绕并突出超出颗粒供应管的端部，以产生围绕喷射颗粒的气帘。 可以使用加热器，隔热构件或不断泄漏的空气来防止管道中的冻结。
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公开(公告)号：US08569824B2
公开(公告)日：2013-10-29
申请号：US12360488
申请日：2009-01-27
IPC分类号： H01L29/792
CPC分类号： H01L27/11568
摘要： The semiconductor device includes: a plurality of bit lines formed in stripes in a semiconductor substrate of a first conductivity type, each of the bit lines being a diffusion layer of an impurity of a second conductivity type; a plurality of gate insulation films formed on regions of the semiconductor substrate between the bit lines; a plurality of word lines formed on the semiconductor substrate via the gate insulating films, the word lines extending in a direction intersecting with the bit lines; and a plurality of bit line isolation diffusion layers formed in regions of the semiconductor substrate between the word lines, each of the bit line isolation diffusion layers being a diffusion layer of an impurity of the first conductivity type. The bit line isolation diffusion layer includes a diffusion suppressor for suppressing diffusion of an impurity.
摘要翻译： 半导体器件包括：在第一导电类型的半导体衬底中以条纹形成的多个位线，每个位线是第二导电类型的杂质的扩散层; 形成在位线之间的半导体衬底的区域上的多个栅极绝缘膜; 经由所述栅极绝缘膜形成在所述半导体衬底上的多个字线，所述字线在与所述位线相交的方向上延伸; 以及在所述字线之间的所述半导体衬底的区域中形成的多个位线隔离扩散层，所述位线隔离扩散层中的每一个为所述第一导电类型的杂质的扩散层。 位线隔离扩散层包括用于抑制杂质扩散的扩散抑制器。
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