公开(公告)号：US09524795B2

公开(公告)日：2016-12-20

申请号：US14847160

申请日：2015-09-08

申请人： Joon-Hyung Lee ,  Oh-Kyum Kwon

发明人： Joon-Hyung Lee ,  Oh-Kyum Kwon

IPC分类号： G11C17/16 ,  G11C17/18

CPC分类号： G11C17/18 ,  G11C17/16

摘要： A one-time programmable (OTP) memory device includes a memory cell array including a plurality of OTP memory cells, the plurality of OTP memory cells being connected to a plurality of bitlines, a plurality of voltage wordlines and a plurality of read wordlines, respectively; and a switching circuit configured to, in a program mode, detect program states of the plurality of OTP memory cells to block currents from flowing through the plurality of OTP memory cells from the voltage wordlines to the bitlines based on the detected program states.

摘要翻译： 一次性可编程（OTP）存储器件包括包括多个OTP存储器单元的存储单元阵列，多个OTP存储器单元分别连接到多个位线，多个电压字线和多个读字线 ; 以及开关电路，被配置为在程序模式下，基于检测到的程序状态，检测多个OTP存储器单元的程序状态以阻止电流从电压字线流过多个OTP存储单元到位线。

公开(公告)号：US20160148705A1

公开(公告)日：2016-05-26

申请号：US14847160

申请日：2015-09-08

申请人： Joon-Hyung LEE ,  Oh-Kyum KWON

发明人： Joon-Hyung LEE ,  Oh-Kyum KWON

IPC分类号： G11C17/18 ,  G11C17/16

CPC分类号： G11C17/18 ,  G11C17/16

摘要： A one-time programmable (OTP) memory device includes a memory cell array including a plurality of OTP memory cells, the plurality of OTP memory cells being connected to a plurality of bitlines, a plurality of voltage wordlines and a plurality of read wordlines, respectively; and a switching circuit configured to, in a program mode, detect program states of the plurality of OTP memory cells to block currents from flowing through the plurality of OTP memory cells from the voltage wordlines to the bitlines based on the detected program states.

摘要翻译： 一次性可编程（OTP）存储器件包括包括多个OTP存储器单元的存储单元阵列，多个OTP存储器单元分别连接到多个位线，多个电压字线和多个读字线 ; 以及开关电路，被配置为在程序模式下，基于检测到的程序状态，检测多个OTP存储器单元的程序状态以阻止电流从电压字线流过多个OTP存储单元到位线。

公开(公告)号：US08525273B2

公开(公告)日：2013-09-03

申请号：US13017984

申请日：2011-01-31

申请人： Oh-kyum Kwon ,  Tae-jung Lee ,  Sun-hyun Kim

发明人： Oh-kyum Kwon ,  Tae-jung Lee ,  Sun-hyun Kim

IPC分类号： H01L27/088

CPC分类号： H01L27/088 ,  H01L21/76229 ,  H01L21/823462 ,  H01L21/823481 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit device includes a substrate having adjacent first and second regions, and a device isolation structure in the substrate between the first and second regions. The first and second regions of the substrate may respectively include transistors configured to be driven at different operational voltages, and the device isolation structure may electrically separates the transistors of the first region from the transistors of the second region. The device isolation structure includes outer portions immediately adjacent to the first and second regions and an inner portion therebetween. The outer portions of the device isolation structure comprise a material having an etching selectivity with respect to that of the inner portion. Related devices and fabrication methods are also discussed.

摘要翻译： 集成电路器件包括具有相邻的第一和第二区域的衬底，以及在第一和第二区域之间的衬底中的器件隔离结构。 衬底的第一和第二区域可以分别包括被配置为以不同的工作电压驱动的晶体管，并且器件隔离结构可以将第一区域的晶体管与第二区域的晶体管电隔离。 装置隔离结构包括紧邻第一和第二区域的外部部分和它们之间的内部部分。 器件隔离结构的外部部分包括相对于内部部分具有蚀刻选择性的材料。 还讨论了相关设备和制造方法。

公开(公告)号：US20080293205A1

公开(公告)日：2008-11-27

申请号：US12125224

申请日：2008-05-22

申请人： Oh-Kyum KWON ,  Bum-Seok KIM ,  Geun-Sook PARK ,  Joon-Suk OH ,  Hye-Young PARK ,  Min-Jun CHOI

发明人： Oh-Kyum KWON ,  Bum-Seok KIM ,  Geun-Sook PARK ,  Joon-Suk OH ,  Hye-Young PARK ,  Min-Jun CHOI

IPC分类号： H01L21/336 ,  H01L21/44

CPC分类号： H01L29/872 ,  H01L21/28518 ,  H01L21/28537 ,  H01L21/324 ,  H01L29/0638 ,  H01L29/0692 ,  H01L29/66143 ,  H01L29/665

摘要： A method of forming a metal silicide layer includes sequentially forming a metal layer and a first capping layer on a substrate, performing a first heat treatment on the substrate to cause the substrate to react to the metal layer, removing the first, capping layer and an unreacted metal layer, forming a second capping layer on the substrate, and performing a second heat treatment on the substrate to form a metal silicide layer on the substrate.

摘要翻译： 形成金属硅化物层的方法包括在基板上依次形成金属层和第一覆盖层，在基板上进行第一热处理以使基板与金属层反应，去除第一封盖层和 未反应的金属层，在衬底上形成第二覆盖层，并在衬底上进行第二热处理，以在衬底上形成金属硅化物层。

公开(公告)号：US08587045B2

公开(公告)日：2013-11-19

申请号：US13181700

申请日：2011-07-13

申请人： Oh-Kyum Kwon ,  Tae-Jung Lee ,  Kyoung-Eun Uhn ,  Byung-Sun Kim

发明人： Oh-Kyum Kwon ,  Tae-Jung Lee ,  Kyoung-Eun Uhn ,  Byung-Sun Kim

IPC分类号： H01L27/108 ,  H01L29/94

CPC分类号： H01L29/78 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11529 ,  H01L27/11558 ,  H01L29/94

摘要： A nonvolatile memory device has a first active region and a second active region defined in a substrate by a device isolation layer, a Metal Oxide Silicon Field-Effect Transistor (MOSFET) disposed on the first active region and including a first electrode pattern, and a Metal Oxide Silicon (MOS) capacitor disposed on the second active region and including a second electrode pattern, and in which the first electrode pattern is narrower in the widthwise direction of the channel of the MOSFET than the first active region.

公开(公告)号：US07705409B2

公开(公告)日：2010-04-27

申请号：US12014244

申请日：2008-01-15

申请人： Oh-kyum Kwon ,  Yong-chan Kim ,  Joon-suk Oh ,  Myung-hee Kim ,  Hye-young Park

发明人： Oh-kyum Kwon ,  Yong-chan Kim ,  Joon-suk Oh ,  Myung-hee Kim ,  Hye-young Park

IPC分类号： H01L29/78

CPC分类号： H01L29/78 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/66568

摘要： Some embodiments of the present invention provide high voltage transistors including a semiconductor substrate and a device isolation film defining an active region in the semiconductor substrate. A gate electrode extends along a central portion of the active region while maintaining a predetermined width on the semiconductor substrate. A second well is formed on both sides of the gate electrode in the semiconductor substrate, and partially extends to a bottom surface of the device isolation film. The active region in the semiconductor substrate comprises a first active region disposed under the gate electrode, and separating the device isolation film and a second active region defined by the first active region and the device isolation film. Methods of manufacturing high voltage transistors are also provided.

摘要翻译： 本发明的一些实施例提供了包括半导体衬底和限定半导体衬底中的有源区的器件隔离膜的高压晶体管。 栅电极沿着有源区的中心部分延伸，同时保持半导体衬底上的预定宽度。 第二阱形成在半导体衬底中的栅电极的两侧，并且部分地延伸到器件隔离膜的底表面。 半导体衬底中的有源区域包括设置在栅电极下方的第一有源区，以及分离器件隔离膜和由第一有源区和器件隔离膜限定的第二有源区。 还提供制造高压晶体管的方法。

公开(公告)号：US20080185664A1

公开(公告)日：2008-08-07

申请号：US12014244

申请日：2008-01-15

申请人： Oh-kyum Kwon ,  Yong-chan Kim ,  Joon-suk Oh ,  Myung-hee Kim ,  Hye-young Park

发明人： Oh-kyum Kwon ,  Yong-chan Kim ,  Joon-suk Oh ,  Myung-hee Kim ,  Hye-young Park

IPC分类号： H01L29/78

CPC分类号： H01L29/78 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/66568

摘要： Some embodiments of the present invention provide high voltage transistors including a semiconductor substrate and a device isolation film defining an active region in the semiconductor substrate. A gate electrode extends along a central portion of the active region while maintaining a predetermined width on the semiconductor substrate. A second well is formed on both sides of the gate electrode in the semiconductor substrate, and partially extends to a bottom surface of the device isolation film. The active region in the semiconductor substrate comprises a first active region disposed under the gate electrode, and separating the device isolation film and a second active region defined by the first active region and the device isolation film. Methods of manufacturing high voltage transistors are also provided.

摘要翻译： 本发明的一些实施例提供了包括半导体衬底和限定半导体衬底中的有源区的器件隔离膜的高压晶体管。 栅电极沿着有源区的中心部分延伸，同时保持半导体衬底上的预定宽度。 第二阱形成在半导体衬底中的栅电极的两侧，并且部分地延伸到器件隔离膜的底表面。 半导体衬底中的有源区域包括设置在栅电极下方的第一有源区，以及分离器件隔离膜和由第一有源区和器件隔离膜限定的第二有源区。 还提供制造高压晶体管的方法。

公开(公告)号：US20120037971A1

公开(公告)日：2012-02-16

申请号：US13181700

申请日：2011-07-13

申请人： Oh-Kyum Kwon ,  Tae-Jung Lee ,  Kyoung-Eun Uhn ,  Byung-Sun Kim

发明人： Oh-Kyum Kwon ,  Tae-Jung Lee ,  Kyoung-Eun Uhn ,  Byung-Sun Kim

IPC分类号： H01L29/78 ,  H01L27/06 ,  H01L29/94

CPC分类号： H01L29/78 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11529 ,  H01L27/11558 ,  H01L29/94

摘要： A nonvolatile memory device has a first active region and a second active region defined in a substrate by a device isolation layer, a Metal Oxide Silicon Field-Effect Transistor (MOSFET) disposed on the first active region and including a first electrode pattern, and a Metal Oxide Silicon (MOS) capacitor disposed on the second active region and including a second electrode pattern, and in which the first electrode pattern is narrower in the widthwise direction of the channel of the MOSFET than the first active region.

摘要翻译： 非易失性存储器件具有通过器件隔离层在衬底中限定的第一有源区和第二有源区，设置在第一有源区上并包括第一电极图的金属氧化物半导体场效应晶体管（MOSFET） 金属氧化物硅（MOS）电容器，其设置在第二有源区并且包括第二电极图案，并且其中第一电极图案在MOSFET的沟道的宽度方向上比第一有源区域窄。

公开(公告)号：US08018021B2

公开(公告)日：2011-09-13

申请号：US12662452

申请日：2010-04-19

申请人： Dae-Shik Kim ,  Oh-Kyum Kwon ,  Myung-Hee Kim ,  Yong-Chan Kim ,  Hye-Young Park ,  Joon-Suk Oh

发明人： Dae-Shik Kim ,  Oh-Kyum Kwon ,  Myung-Hee Kim ,  Yong-Chan Kim ,  Hye-Young Park ,  Joon-Suk Oh

IPC分类号： H01L29/872

CPC分类号： H01L29/872 ,  H01L29/0619 ,  H01L29/0649 ,  H01L29/47 ,  H01L29/66143

摘要： A schottky diode may include a schottky junction including a well formed in a semiconductor substrate and a first electrode contacting the first well. The well may have a first conductivity type. A first ohmic junction may include a first junction region formed in the well and a second electrode contacting the first junction region. The first junction region may have a higher concentration of the first conductivity type than the well. A first device isolation region may be formed in the semiconductor substrate separating the schottky junction and the first ohmic junction. A well guard having a second conductivity type opposite to the first conductivity type may be formed in the well. At least a portion of the well guard may be formed under a portion of the schottky junction.

摘要翻译： 肖特基二极管可以包括包括在半导体衬底中形成的阱和与第一阱接触的第一电极的肖特基结。 该井可具有第一导电类型。 第一欧姆结可以包括形成在阱中的第一结区域和与第一结区接触的第二电极。 第一结区可能具有比阱更高的第一导电类型的浓度。 可以在分离肖特基结和第一欧姆结的半导体衬底中形成第一器件隔离区。 可以在井中形成具有与第一导电类型相反的第二导电类型的保护罩。 阱护套的至少一部分可以形成在肖特基结的一部分下方。

公开(公告)号：US20080006899A1

公开(公告)日：2008-01-10

申请号：US11797560

申请日：2007-05-04

申请人： Dae-Shik Kim ,  Oh-Kyum Kwon ,  Myung-Hee Kim ,  Yong-Chan Kim ,  Hye-Young Park ,  Joon-Suk Oh

发明人： Dae-Shik Kim ,  Oh-Kyum Kwon ,  Myung-Hee Kim ,  Yong-Chan Kim ,  Hye-Young Park ,  Joon-Suk Oh

IPC分类号： H01L29/47 ,  H01L21/28

CPC分类号： H01L29/872 ,  H01L29/0619 ,  H01L29/0649 ,  H01L29/47 ,  H01L29/66143

摘要： A schottky diode may include a schottky junction including a well formed in a semiconductor substrate and a first electrode contacting the first well. The well may have a first conductivity type. A first ohmic junction may include a first junction region formed in the well and a second electrode contacting the first junction region. The first junction region may have a higher concentration of the first conductivity type than the well. A first device isolation region may be formed in the semiconductor substrate separating the schottky junction and the first ohmic junction. A well guard having a second conductivity type opposite to the first conductivity type may be formed in the well. At least a portion of the well guard may, be formed under a portion of the schottky junction.

摘要翻译： 肖特基二极管可以包括包括在半导体衬底中形成的阱和与第一阱接触的第一电极的肖特基结。 该井可具有第一导电类型。 第一欧姆结可以包括形成在阱中的第一结区域和与第一结区接触的第二电极。 第一结区可能具有比阱更高的第一导电类型的浓度。 可以在分离肖特基结和第一欧姆结的半导体衬底中形成第一器件隔离区。 可以在井中形成具有与第一导电类型相反的第二导电类型的保护罩。 可以在肖特基结的一部分下方形成阱护罩的至少一部分。