公开(公告)号：US08525273B2

公开(公告)日：2013-09-03

申请号：US13017984

申请日：2011-01-31

申请人： Oh-kyum Kwon ,  Tae-jung Lee ,  Sun-hyun Kim

发明人： Oh-kyum Kwon ,  Tae-jung Lee ,  Sun-hyun Kim

IPC分类号： H01L27/088

CPC分类号： H01L27/088 ,  H01L21/76229 ,  H01L21/823462 ,  H01L21/823481 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit device includes a substrate having adjacent first and second regions, and a device isolation structure in the substrate between the first and second regions. The first and second regions of the substrate may respectively include transistors configured to be driven at different operational voltages, and the device isolation structure may electrically separates the transistors of the first region from the transistors of the second region. The device isolation structure includes outer portions immediately adjacent to the first and second regions and an inner portion therebetween. The outer portions of the device isolation structure comprise a material having an etching selectivity with respect to that of the inner portion. Related devices and fabrication methods are also discussed.

摘要翻译： 集成电路器件包括具有相邻的第一和第二区域的衬底，以及在第一和第二区域之间的衬底中的器件隔离结构。 衬底的第一和第二区域可以分别包括被配置为以不同的工作电压驱动的晶体管，并且器件隔离结构可以将第一区域的晶体管与第二区域的晶体管电隔离。 装置隔离结构包括紧邻第一和第二区域的外部部分和它们之间的内部部分。 器件隔离结构的外部部分包括相对于内部部分具有蚀刻选择性的材料。 还讨论了相关设备和制造方法。

公开(公告)号：US20130313654A1

公开(公告)日：2013-11-28

申请号：US13955737

申请日：2013-07-31

申请人： Oh-kyum Kwon ,  Tae-jung Lee ,  Sun-hyun Kim

发明人： Oh-kyum Kwon ,  Tae-jung Lee ,  Sun-hyun Kim

IPC分类号： H01L27/088

CPC分类号： H01L27/088 ,  H01L21/76229 ,  H01L21/823462 ,  H01L21/823481 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit device includes a substrate having adjacent first and second regions, and a device isolation structure in the substrate between the first and second regions. The first and second regions of the substrate may respectively include transistors configured to be driven at different operational voltages, and the device isolation structure may electrically separates the transistors of the first region from the transistors of the second region. The device isolation structure includes outer portions immediately adjacent to the first and second regions and an inner portion therebetween. The outer portions of the device isolation structure comprise a material having an etching selectivity with respect to that of the inner portion. Related devices and fabrication methods are also discussed.

摘要翻译： 集成电路器件包括具有相邻的第一和第二区域的衬底，以及在第一和第二区域之间的衬底中的器件隔离结构。 衬底的第一和第二区域可以分别包括被配置为以不同的工作电压驱动的晶体管，并且器件隔离结构可以将第一区域的晶体管与第二区域的晶体管电隔离。 装置隔离结构包括紧邻第一和第二区域的外部部分和它们之间的内部部分。 器件隔离结构的外部部分包括相对于内部部分具有蚀刻选择性的材料。 还讨论了相关设备和制造方法。

公开(公告)号：US20120032269A1

公开(公告)日：2012-02-09

申请号：US13272675

申请日：2011-10-13

申请人： Dong-ryul Chang ,  Tae-jung Lee ,  Sung-hoan Kim ,  Soo-cheol Lee

发明人： Dong-ryul Chang ,  Tae-jung Lee ,  Sung-hoan Kim ,  Soo-cheol Lee

IPC分类号： H01L29/78

CPC分类号： H01L21/823871 ,  H01L21/823857 ,  H01L21/823878 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided are a semiconductor integrated device and a method for fabricating the same. The semiconductor integrated circuit includes a semiconductor substrate including a first dopant, a first conductive layer pattern formed on the semiconductor substrate, an interlayer dielectric layer formed on the first conductive layer pattern, a second conductive layer pattern formed on the interlayer dielectric layer, and a first vacuum ultraviolet (VUV) blocking layer which blocks a VUV ray radiated to the semiconductor substrate.

摘要翻译： 提供一种半导体集成器件及其制造方法。 半导体集成电路包括：半导体衬底，包括第一掺杂剂，形成在半导体衬底上的第一导电层图案，形成在第一导电层图案上的层间绝缘层，形成在层间绝缘层上的第二导电层图案;以及 第一真空紫外线（VUV）阻挡层，其阻挡辐射到半导体衬底的VUV射线。

公开(公告)号：US07593261B2

公开(公告)日：2009-09-22

申请号：US11643837

申请日：2006-12-22

申请人： Geun-sook Park ,  Sang-bae Yi ,  Soo-cheol Lee ,  Ho-ik Hwang ,  Tae-jung Lee

发明人： Geun-sook Park ,  Sang-bae Yi ,  Soo-cheol Lee ,  Ho-ik Hwang ,  Tae-jung Lee

IPC分类号： G11C11/03

CPC分类号： H01L27/11558 ,  H01L27/115 ,  H01L27/11521

摘要： An electrically erasable and programmable read-only memory (EEPROM) is provided. The EEPROM includes a semiconductor substrate including spaced apart first, second and third active regions, a common floating gate traversing over the first through third active regions, source/drain regions formed in the third active region on opposite sides of the floating gate, a first interconnect connected to the first active region, a second interconnect connected to the second active region, and a third interconnect connected to either one of the source/drain regions.

摘要翻译： 提供电可擦除和可编程只读存储器（EEPROM）。 EEPROM包括半导体衬底，其包括间隔开的第一，第二和第三有源区域，跨越第一至第三有源区域的公共浮动栅极，形成在浮置栅极的相对侧上的第三有源区域中的源极/漏极区域，第一 连接到第一有源区的互连，连接到第二有源区的第二互连以及连接到源/漏区中的任一个的第三互连。

公开(公告)号：US07348241B2

公开(公告)日：2008-03-25

申请号：US11384727

申请日：2006-03-20

申请人： Joon-hyung Lee ,  Byung-sun Kim ,  Tae-jung Lee

发明人： Joon-hyung Lee ,  Byung-sun Kim ,  Tae-jung Lee

IPC分类号： H01L21/336

CPC分类号： H01L21/28273 ,  H01L29/42324 ,  H01L29/513 ,  H01L29/66825 ,  H01L29/7881

摘要： Provided are a cell structure of an EPROM device and a method for fabricating the same. The cell structure includes a gate stack, which includes a first floating gate, an insulating pattern including a nitride layer, and a control gate that are sequentially stacked on a semiconductor substrate, and includes a window for exposing the top surface or both sidewalls of the first floating gate on both sides of the control gate, so that charges of the first floating gate can be erased by ultraviolet rays. The cell structure further includes a floating gate transistor, which includes a gate insulating layer formed on the semiconductor substrate, a second floating gate that is formed on the gate insulating layer and is connected to the first floating gate in the gate stack, and a source/drain that is formed in the semiconductor substrate so as to be aligned to the second floating gate. In the cell structure, the window is formed on the top surface or both sidewalls of the first floating gate of the gate stack. Thus, ultraviolet rays can penetrate through the window and easily erase charges of the programmed cell.

摘要翻译： 提供EPROM器件的单元结构及其制造方法。 电池结构包括栅极堆叠，其包括第一浮置栅极，包括氮化物层的绝缘图案和顺序地堆叠在半导体衬底上的控制栅极，并且包括用于暴露所述顶部表面或两个侧壁的窗口 第一个浮动栅极位于控制栅极的两侧，使得第一个浮动栅极的电荷可以被紫外线消除。 电池结构还包括浮栅晶体管，其包括形成在半导体衬底上的栅极绝缘层，形成在栅极绝缘层上并连接到栅堆叠中的第一浮栅的第二浮栅，以及源极 /漏极，其形成在半导体衬底中以便与第二浮栅对准。 在电池结构中，窗口形成在栅堆叠的第一浮栅的顶表面或两个侧壁上。 因此，紫外线可以穿过窗口并容易地擦除编程单元的电荷。

公开(公告)号：US06653180B2

公开(公告)日：2003-11-25

申请号：US10140711

申请日：2002-05-08

申请人： Tae-jung Lee

发明人： Tae-jung Lee

IPC分类号： H01L2100

CPC分类号： H01L21/823857

摘要： An electronic device on a semiconductor substrate can include first and second field effect transistors on a substrate. In particular, the first field effect transistor includes a first gate dielectric layer having a first nitrogen concentration, and the second field effect transistor includes a second gate dielectric layer having a second nitrogen concentration lower than the first nitrogen concentration. More particularly, the first field effect transistor can be a PMOS transistor, and the second field effect transistor can be an NMOS transistor. Related methods are also discussed.

公开(公告)号：US08143690B2

公开(公告)日：2012-03-27

申请号：US12219336

申请日：2008-07-21

申请人： Myoung-kyu Park ,  Byung-sun Kim ,  Tae-jung Lee ,  Kee-in Bang

发明人： Myoung-kyu Park ,  Byung-sun Kim ,  Tae-jung Lee ,  Kee-in Bang

IPC分类号： H01L27/06

CPC分类号： H01L27/0814 ,  H01L27/0255

摘要： Semiconductor device having an on-chip type electrostatic discharge (ESD) protection circuit and a method of manufacturing the same are provided. The on-chip type ESD protection circuit may include a first junction diode having a first conductive type region contacting a second conductive type region in a semiconductor substrate, and a first schottky diode having a metallic material layer arranged on and contacting the first conductive type region of the semiconductor substrate.

摘要翻译： 提供具有片上型静电放电（ESD）保护电路的半导体器件及其制造方法。 片上型ESD保护电路可以包括具有与半导体衬底中的第二导电类型区域接触的第一导电类型区域的第一结二极管和具有布置在第一导电类型区域上并与第一导电类型区域接触的金属材料层的第一肖特基二极管 的半导体衬底。

公开(公告)号：US20080057689A1

公开(公告)日：2008-03-06

申请号：US11977039

申请日：2007-10-23

申请人： Dong-ryul Chang ,  Tae-jung Lee ,  Sung-hoan Kim ,  Soo-cheol Lee

发明人： Dong-ryul Chang ,  Tae-jung Lee ,  Sung-hoan Kim ,  Soo-cheol Lee

IPC分类号： H01L21/3205

CPC分类号： H01L21/823871 ,  H01L21/823857 ,  H01L21/823878 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided are a semiconductor integrated device and a method for fabricating the same. The semiconductor integrated circuit includes a semiconductor substrate including a first dopant, a first conductive layer pattern formed on the semiconductor substrate, an interlayer dielectric layer formed on the first conductive layer pattern, a second conductive layer pattern formed on the interlayer dielectric layer, and a first vacuum ultraviolet (VUV) blocking layer which blocks a VUV ray radiated to the semiconductor substrate.

摘要翻译： 提供一种半导体集成器件及其制造方法。 半导体集成电路包括：半导体衬底，包括第一掺杂剂，形成在半导体衬底上的第一导电层图案，形成在第一导电层图案上的层间绝缘层，形成在层间绝缘层上的第二导电层图案;以及 第一真空紫外线（VUV）阻挡层，其阻挡辐射到半导体衬底的VUV射线。

公开(公告)号：US06885609B2

公开(公告)日：2005-04-26

申请号：US10724687

申请日：2003-12-02

申请人： Tae-jung Lee ,  Byung-sun Kim ,  Joon-hyung Lee

发明人： Tae-jung Lee ,  Byung-sun Kim ,  Joon-hyung Lee

IPC分类号： G11C11/41 ,  G11C8/16 ,  G11C11/40 ,  G11C11/412 ,  H01L21/8244 ,  H01L27/11 ,  G11C8/00 ,  G11C11/00

CPC分类号： G11C8/16

摘要： A layout of a memory cell of a dual-port semiconductor memory device provides for one memory cell that includes a total of eight transistors, including two NMOS scan transistors. Among the transistors, two PMOS transistors and six NMOS transistors are disposed in one N-well area and one contiguous P-well area of a semiconductor substrate, respectively. The N-well area is disposed at a corner of the memory cell for improving efficiency of the layout. Since one N-well area and one P-well area are formed in the semiconductor substrate, the size of an isolated area between the N-well area and the P-well area can be reduced, thus also reducing the size of a memory cell.

摘要翻译： 双端口半导体存储器件的存储单元的布局提供了一个存储单元，其包括总共八个晶体管，包括两个NMOS扫描晶体管。 在晶体管中，两个PMOS晶体管和六个NMOS晶体管分别设置在半导体衬底的一个N阱区域和一个邻接的P阱区域中。 N阱区域设置在存储单元的拐角处，以提高布局的效率。 由于在半导体衬底中形成一个N阱区和一个P阱区，所以可以减小N阱区和P阱区之间的隔离区的大小，从而也减小了存储单元的尺寸 。

公开(公告)号：US06410375B1

公开(公告)日：2002-06-25

申请号：US09358574

申请日：1999-07-21

申请人： Tae-jung Lee

发明人： Tae-jung Lee

IPC分类号： H01L218238

CPC分类号： H01L21/823857

摘要： A method of forming an electronic device on a semiconductor substrate includes forming first and second field effect transistors on a substrate. In particular, the first field effect transistor includes a first gate dielectric layer having a first nitrogen concentration, and the second field effect transistor includes a second gate dielectric layer having a second nitrogen concentration lower than the first nitrogen concentration. More particularly, the first field effect transistor can be a PMOS transistor, and the second field effect transistor can be an NMOS transistor. Related structures are also discussed.

摘要翻译： 在半导体衬底上形成电子器件的方法包括在衬底上形成第一和第二场效应晶体管。 特别地，第一场效应晶体管包括具有第一氮浓度的第一栅介质层，第二场效应晶体管包括具有低于第一氮浓度的第二氮浓度的第二栅介质层。 更具体地，第一场效应晶体管可以是PMOS晶体管，并且第二场效应晶体管可以是NMOS晶体管。 还讨论了相关结构。