公开(公告)号：US06298000B1

公开(公告)日：2001-10-02

申请号：US08515767

申请日：1995-08-15

申请人： Osamu Kitade ,  Takahiro Komatsu

发明人： Osamu Kitade ,  Takahiro Komatsu

IPC分类号： G11C1100

CPC分类号： G11C11/406

摘要： A power supply voltage detecting circuit detects whether or not a power supply voltage Vcc is a predetermined reference voltage level or more. The power supply voltage detecting circuit generates a self-refresh mode instruct signal &phgr;A to apply the same to a refresh timer when the power supply voltage detecting circuit determine that the power supply voltage Vcc is a predetermined voltage value or less. The refresh timer carries out a clocking operation in response to the self-refresh mode instruct signal &phgr;A to generate a self-refresh request signal &phgr;srf at a predetermined time interval. A semiconductor memory device is implemented which can carry out the self-refresh mode easily without requiring a complicated timing condition of external signals.

摘要翻译： 电源电压检测电路检测电源电压Vcc是否为预定的参考电压电平以上。 当电源电压检测电路确定电源电压Vcc是预定电压值或更小时，电源电压检测电路产生自刷新模式指令信号phiA以将其施加到刷新定时器。 刷新定时器响应于自刷新模式指令信号phiA执行时钟操作，以预定时间间隔生成自刷新请求信号phisrf。 实现了可以容易地执行自刷新模式而不需要外部信号的复杂定时条件的半导体存储器件。

公开(公告)号：US06327208B1

公开(公告)日：2001-12-04

申请号：US09645610

申请日：2000-08-25

申请人： Osamu Kitade

发明人： Osamu Kitade

IPC分类号： G11C700

CPC分类号： G11C7/222 ,  G11C11/406

摘要： In an REFS generation circuit included in a self refresh circuit of a DRAM, first to fifth N channel MOS transistors are connected in parallel with first to fifth fuses, and first to fifth P channel MOS transistors are connected in series with the first to fifth fuses. If the first to third and fifth fuses are blown to select a fourth clock signal and then the refresh performance is lowered, a third clock signal, for example, having a frequency shorter than the fourth clock signal is selected by rendering conductive only the third N channel MOS transistor and the third P channel MOS transistor of first to fifth N channel MOS transistors and the first to fifth P channel MOS transistors. Therefore, the refresh cycle can be shortened and a DRAM with a refresh failure can be repaired.

摘要翻译： 在包括在DRAM的自刷新电路中的REFS生成电路中，第一至第五N沟道MOS晶体管与第一至第五保险丝并联连接，并且第一至第五P沟道MOS晶体管与第一至第五保险丝串联连接 。 如果第一至第三和第五保险丝被熔断以选择第四时钟信号，然后刷新性能降低，则通过仅导通第三个N选择具有比第四时钟信号更短的频率的第三时钟信号 第一至第五N沟道MOS晶体管和第一至第五P沟道MOS晶体管的第三P沟道MOS晶体管。 因此，可以缩短刷新周期，并且可以修复具有刷新故障的DRAM。

公开(公告)号：US06434070B1

公开(公告)日：2002-08-13

申请号：US09909976

申请日：2001-07-23

申请人： Hiroshi Itou ,  Osamu Kitade

发明人： Hiroshi Itou ,  Osamu Kitade

IPC分类号： G11C700

CPC分类号： G11C29/006 ,  G11C29/02

摘要： The VBL variable circuit is provided with a VBL generating circuit, a test mode judging circuit, a large pump and a small pump, and makes a voltage for precharging a bit line variable. Thus, a defective bit line having little margin with respect to a bit line precharging voltage of a high level or a low level can be detected.

摘要翻译： VBL可变电路具有VBL发生电路，测试模式判断电路，大型泵和小型泵，并且对位线变量进行预充电。 因此，可以检测到相对于高电平或低电平的位线预充电电压具有很小余量的有缺陷位线。

公开(公告)号：US06417726B1

公开(公告)日：2002-07-09

申请号：US09846196

申请日：2001-05-02

申请人： Osamu Kitade

发明人： Osamu Kitade

IPC分类号： H03K1772

CPC分类号： G11C29/021 ,  G11C5/147 ,  G11C11/4074 ,  G11C29/02 ,  G11C2029/5004 ,  H02J1/04 ,  H02M2001/0025

摘要： A reference potential is generated according to a potential Viconst output from a constant current control circuit, and an internal power supply potential is generated based on the reference potential. Fuse elements are provided in the constant current control circuit. Since the resistance value of a resistance circuit can be adjusted, an internal power supply potential can be adjusted in a wider range than that in a conventional circuit. Reduction in yield can be prevented in the case where a threshold voltage or the like is varied.

摘要翻译： 根据来自恒定电流控制电路的潜在Viconst输出产生参考电位，并且基于参考电位产生内部电源电位。 在恒流控制电路中提供保险丝元件。 由于可以调节电阻电路的电阻值，所以可以在比现有电路更宽的范围内调整内部电源电位。 在阈值电压等变化的情况下，可以防止产量的降低。

公开(公告)号：US06414888B2

公开(公告)日：2002-07-02

申请号：US09212310

申请日：1998-12-16

申请人： Osamu Kitade ,  Tetsushi Hoshita

发明人： Osamu Kitade ,  Tetsushi Hoshita

IPC分类号： G11C700

CPC分类号： G11C29/50 ,  G11C11/401

摘要： A semiconductor storage device having a line-to-line burn-in function of main word lines, applying a stress voltage between the main word lines in a wafer burn-in state. In a wafer burn-in state, by a control circuit means, main word lines are divided to odd-numbered lines and even-numbered lines to be connected to an odd-numbered pad and an even-numbered pad respectively, and a stress voltage is applied directly between the odd-numbered pad and the even-numbered pad. By a row decoder being capable of control in both of an ordinary operation mode and a wafer burn-in operation mode, in a wafer burn-in state, main word lines are divided to odd-numbered lines and even-numbered lines to become selective state, and a stress voltage is applied between main word lines.

摘要翻译： 一种具有主字线的线间老化功能的半导体存储装置，在晶片老化状态下在主字线之间施加应力电压。 在晶片老化状态下，通过控制电路装置将主字线划分为奇数行和偶数行，分别连接到奇数编号的焊盘和偶数焊盘，应力电压 直接施加在奇数编号的垫和偶数垫之间。 通过能够在普通操作模式和晶片老化操作模式中进行控制的行解码器，在晶片老化状态下，将主字线划分为奇数行和偶数行以选择 状态，并且在主字线之间施加应力电压。

公开(公告)号：US06314035B1

公开(公告)日：2001-11-06

申请号：US09615954

申请日：2000-07-13

申请人： Osamu Kitade ,  Tetsushi Hoshita

发明人： Osamu Kitade ,  Tetsushi Hoshita

IPC分类号： G11C700

CPC分类号： G11C29/02

摘要： In a semiconductor memory device a column decoder outputs column select signals which are in turn transmitted to a memory cell block via a transfer gate which turns on when a signal fed through a WBI pad is placed in the inactive state. Even-numbered column select lines are connected via a transfer gate to an even-numbered CSL pad, and odd-numbered column select lines are connected via the transfer gate to an odd-numbered CSL pad.

摘要翻译： 在半导体存储器件中，列解码器输出列选择信号，而这些列选择信号又通过传送门发送到存储器单元块，当通过WBI焊盘馈送的信号处于非活动状态时，该选通信号接通。 偶数列选择线通过传输门连接到偶数CSL焊盘，奇数列选择线通过传输门连接到奇数编号的CSL焊盘。

公开(公告)号：US06340823B1

公开(公告)日：2002-01-22

申请号：US09215200

申请日：1998-12-18

申请人： Osamu Kitade

发明人： Osamu Kitade

IPC分类号： H01C2358

CPC分类号： H01L22/32 ,  G01R31/2884 ,  G01R31/2886 ,  G01R31/318505 ,  G01R31/318511 ,  G01R31/31905 ,  H01L2924/0002 ,  H01L2924/00

摘要： There is described a semiconductor wafer suitable for efficiently testing a plurality of logic chips formed thereon without damaging input/output sections of the chips. A plurality of chips, a test circuit, and output pads are formed on a semiconductor wafer. A plurality of input pads of the test circuit are connected to terminals corresponding to all the chips by way of a test pattern. The chips are connected to the output pads by means of test patterns. All the chips are subjected to a test (or multi-test) through use of the test circuit and the output pads. The test circuit and the output pads are provided in the peripheral area of the semiconductor wafer.

摘要翻译： 描述了适于有效测试形成在其上的多个逻辑芯片的半导体晶片，而不损坏芯片的输入/输出部分。 在半导体晶片上形成多个芯片，测试电路和输出焊盘。 测试电路的多个输入焊盘通过测试图案连接到对应于所有芯片的端子。 芯片通过测试模式连接到输出焊盘。 所有的芯片都通过使用测试电路和输出焊盘进行测试（或多重测试）。 测试电路和输出焊盘设置在半导体晶片的周边区域中。

公开(公告)号：US06285222B1

公开(公告)日：2001-09-04

申请号：US09226164

申请日：1999-01-07

申请人： Osamu Kitade

发明人： Osamu Kitade

IPC分类号： H03L700

CPC分类号： H03K17/223

摘要： A /POR circuit which can detect a power-on of a power supply voltage without fail even in a case where a potential of the power supply rises gently and which produces a /POR signal having a waveform sufficient for initializing internal circuits, as well as a semiconductor device having the /POR circuit. In a power-on reset circuit, a first line potential monitoring circuit and a second line potential monitoring circuit detect a line potential, and there is provided in a /POR signal waveform generation circuit a setting circuit which outputs a pulse signal in response to the results of such detection and operates in response to the pulse signal. Even when the potential of a power-on reset signal rises gently at power-on, the power-on reset signal can be brought to an activation potential without fail, thereby initializing internal circuits.

摘要翻译： A / POR电路即使在电源的电位缓缓上升并且产生具有足以初始化内部电路的波形的POR信号的情况下也能够无故障地检测电源电压的通电，以及 具有/ POR电路的半导体器件。 在上电复位电路中，第一线路电位监视电路和第二线路电位监视电路检测线路电位，并且在POR信号波形生成电路中设置有响应于所述线路电位输出脉冲信号的设定电路 这种检测的结果并且响应于脉冲信号而操作。 即使上电复位信号的电位在上电时缓慢上升，上电复位信号也可以无功而复位，从而初始化内部电路。

公开(公告)号：US06225836B1

公开(公告)日：2001-05-01

申请号：US09336710

申请日：1999-06-21

申请人： Osamu Kitade

发明人： Osamu Kitade

IPC分类号： H03K5153

CPC分类号： G11C7/1045

摘要： A semiconductor integrated circuit device includes an operating mode setting circuit for determining an operating mode. Operating mode setting circuit includes an operating mode control circuit and an operating mode alteration circuit. Operating mode control circuit generates an operating mode setting signal depending on wire bonding provided to external input pads. Operating mode alteration circuit includes fuse input pads, electric fuses, and an operating mode inverting circuit. Operating mode inverting circuit inverts an operating mode setting signal once determined by blowing each of electric fuses.

摘要翻译： 半导体集成电路装置包括用于确定操作模式的操作模式设置电路。 操作模式设置电路包括操作模式控制电路和操作模式改变电路。 工作模式控制电路根据提供给外部输入焊盘的引线键合产生工作模式设置信号。 工作模式改变电路包括熔丝输入焊盘，电熔丝和工作模式反相电路。 操作模式反相电路将通过吹入每个电保险丝确定的操作模式设置信号反相。

公开(公告)号：US5694074A

公开(公告)日：1997-12-02

申请号：US580774

申请日：1995-12-29

申请人： Osamu Kitade ,  Yutaka Ikeda

发明人： Osamu Kitade ,  Yutaka Ikeda

IPC分类号： G11C5/14 ,  G11C7/10 ,  H03K5/1252 ,  H03K17/30

CPC分类号： G11C7/1084 ,  G11C5/147 ,  G11C7/1051 ,  G11C7/1078 ,  H03K5/1252

摘要： A semiconductor integrated circuit comprises a NAND gate which constitutes a previous stage circuit, a reset circuit, a charging circuit, and a capacitor for generating a boost potential. A signal of a node A expressing data and a signal of a node B expressing permission of outputting data are not only input to the NAND gate, but also to the reset circuit, and the output of the reset circuit is not only input to the charging circuit but also to the NAND gate; therefore, the previous stage circuit and the reset circuit are interlinked with the output signals. In the result, even in a case where noise is generated in the node A, it is possible to obtain a sufficient boost potential generated in the capacitor.

摘要翻译： 半导体集成电路包括构成前级电路的NAND门，复位电路，充电电路和用于产生升压电位的电容器。 表示数据的节点A的信号和表示允许输出数据的节点B的信号不仅输入到NAND门，而且还输入到复位电路，并且复位电路的输出不仅被输入到充电 电路，也是与NAND门; 因此，前级电路和复位电路与输出信号相互连接。 结果，即使在节点A中产生噪声的情况下，也可以获得在电容器中产生的足够的升压电位。