Abstract:
A chemical-mechanical polishing (CMP) proximity correction method for polishing a wafer is provided. The wafer has a polish area and a protected area. The method includes forming a material layer over the wafer to cover the polish area and the protected area and then forming a protective layer over the material layer. Thereafter, the protective layer is patterned so that the remaining protective layer is at a distance away from the boundary of the polish area to reduce shadowing effects. Because the boundary of the protective layer above the material layer recedes to an area at a distance away from polish area, the whole polish area can be cleanly polished.
Abstract:
A chemical-mechanical polishing (CMP) proximity correction method for polishing a wafer is provided. The wafer has a polish area and a protected area. The method includes forming a material layer over the wafer to cover the polish area and the protected area and then forming a protective layer over the material layer. Thereafter, the protective layer is patterned so that the remaining protective layer is at a distance away from the boundary of the polish area to reduce shadowing effects. Because the boundary of the protective layer above the material layer recedes to an area at a distance away from polish area, the whole polish area can be cleanly polished.
Abstract:
A method for fabricating semiconductor memory cells such as dynamic random access memory (DRAM) and ferroelectric random access memory (FRAM) with improved contact between the capacitor electrode and the underneath device area. It includes the following main steps of: (1) forming a first dielectric layer on a wafer surface; (2) forming at least one through opening in the first dielectric layer; (3) forming a ruthenium based plug in the through opening; and (4) forming a capacitor in contact with the ruthenium based plug. The ruthenium based plug can be made of ruthenium metal, conductive ruthenium oxide, or a stack of conductive ruthenium oxide and ruthenium metal. The method allows the memory cell to be made without the need for a barrier, which is required to protect the storage electrode from reacting with Si atoms during the fabrication process.