公开(公告)号：US06368910B1

公开(公告)日：2002-04-09

申请号：US09721796

申请日：2000-11-24

申请人： Bor-Bu Sheu ,  Chung-Ming Chu ,  Ming-Chung Chiang ,  Min-Chieh Yang ,  Wen-Chung Liu ,  Jong-Bor Wang ,  Pai-Hsuan Sun

发明人： Bor-Bu Sheu ,  Chung-Ming Chu ,  Ming-Chung Chiang ,  Min-Chieh Yang ,  Wen-Chung Liu ,  Jong-Bor Wang ,  Pai-Hsuan Sun

IPC分类号： H01L218242

CPC分类号： H01L28/91 ,  H01L21/76877 ,  H01L23/485 ,  H01L28/55 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for fabricating semiconductor memory cells such as dynamic random access memory (DRAM) and ferroelectric random access memory (FRAM) with improved contact between the capacitor electrode and the underneath device area. It includes the following main steps of: (1) forming a first dielectric layer on a wafer surface; (2) forming at least one through opening in the first dielectric layer; (3) forming a ruthenium based plug in the through opening; and (4) forming a capacitor in contact with the ruthenium based plug. The ruthenium based plug can be made of ruthenium metal, conductive ruthenium oxide, or a stack of conductive ruthenium oxide and ruthenium metal. The method allows the memory cell to be made without the need for a barrier, which is required to protect the storage electrode from reacting with Si atoms during the fabrication process.

摘要翻译： 一种用于制造诸如动态随机存取存储器（DRAM）和铁电随机存取存储器（FRAM）的半导体存储器单元的方法，其具有改善的电容器电极和下面的器件区域之间的接触。 它包括以下主要步骤：（1）在晶片表面上形成第一电介质层; （2）在所述第一电介质层中形成至少一个通孔; （3）在通孔中形成钌基塞; 和（4）形成与钌基塞接触的电容器。 钌基塞可以由钌金属，导电氧化钌或导电氧化钌和金属钌的叠层制成。 该方法允许在不需要屏蔽的情况下制造存储单元，这是在制造过程中保护存储电极不与Si原子反应所需要的。

公开(公告)号：US06977127B2

公开(公告)日：2005-12-20

申请号：US10320243

申请日：2002-12-16

申请人： Chii-Ming Shiah ,  Yi-Yu Hsu ,  Yu-Cheng Tung ,  Hung-Yueh Liao ,  Kao-Tsai Tsai ,  Jong-Bor Wang

发明人： Chii-Ming Shiah ,  Yi-Yu Hsu ,  Yu-Cheng Tung ,  Hung-Yueh Liao ,  Kao-Tsai Tsai ,  Jong-Bor Wang

IPC分类号： G03F1/30 ,  G03F1/68 ,  H01L21/027 ,  G03F9/00 ,  G03C5/00

CPC分类号： G03F1/30

摘要： An alternating phase shift mask. The alternating phase shift mask includes a transparent substrate, a light-shielding layer disposed on the transparent substrate to define a transparent array consisting of a plurality of first phase rows and a plurality of second phase rows alternately interposed between the first phase rows. The alternating phase shift mask further comprises a phase interference enhancement feature disposed a predetermined distance from the outermost row of the transparent array, wherein the phases of the phase interference enhancement feature and the outermost row are reverse.

摘要翻译： 交替相移掩模。 交替相移掩模包括透明基板，设置在透明基板上的遮光层，以限定由多个第一相位行和交替插入在第一相位行之间的多个第二相位行组成的透明阵列。 所述交变相移掩模还包括相对于所述透明阵列的最外侧行预定距离设置的相位干涉增强特征，其中所述相位干扰增强特征和最外侧行的相位相反。

公开(公告)号：US06235621B1

公开(公告)日：2001-05-22

申请号：US09447008

申请日：1999-11-22

申请人： Erik S. Jeng ,  Tzu-Shih Yen ,  Chi-San Wu ,  Jong-Bor Wang

发明人： Erik S. Jeng ,  Tzu-Shih Yen ,  Chi-San Wu ,  Jong-Bor Wang

IPC分类号： H01L213205

CPC分类号： H01L21/28114 ,  H01L21/28061 ,  H01L21/31111 ,  H01L21/76897 ,  H01L29/42376 ,  H01L29/6656

摘要： A method for fabricating semiconductor device is disclosed herein. The first step is to form a first oxide layer on a substrate. Subsequently formed are polycrystalline silicon layer, a polycide layer, optionally a second oxide layer, and a silicon nitride layer on the first oxide layer. A photoresist pattern on the silicon layer is formed thereafter, and the silicon nitride layer is etched using the photoresist pattern as a mask to expose a portion of the polycide layer. The photoresist pattern is then, the polycide layer is isotropically etched to form an under cut in the polycide layer under the etched nitride layer (optional second oxide layer). The width of the top portion of the isotropically etched polycide layer is smaller than the width of the etched nitride layer. The isotropically etched polycide layer is then anistropically etched, and the polycrystalline layer is etched to expose a portion of the first oxide layer to form a multi-layer structure. Finally, spacers on side-walls of the multi-layer structure are formed to create the semiconductor device, the side-wall of the anisotropicaly etched polycide layer generated after the oxidation process is prevented from penetrating the spacer of the semiconductor device according to the present invention.

摘要翻译： 本文公开了半导体器件的制造方法。 第一步是在衬底上形成第一氧化物层。 随后形成的是多晶硅层，多晶硅化物层，任选的第二氧化物层和第一氧化物层上的氮化硅层。 此后形成硅层上的光致抗蚀剂图案，并且使用光致抗蚀剂图案作为掩模蚀刻氮化硅层以暴露多晶硅化物层的一部分。 然后，光致抗蚀剂图案，多孔体层被各向同性地蚀刻以在蚀刻的氮化物层（可选的第二氧化物层）下的多晶硅化物层中形成下切割。 各向同性蚀刻的多晶硅化物层的顶部的宽度小于被蚀刻的氮化物层的宽度。 然后对各向同性蚀刻的多晶硅化物层进行水磨蚀蚀刻，并且蚀刻多晶层以暴露第一氧化物层的一部分以形成多层结构。 最后，形成多层结构的侧壁上的间隔物以形成半导体器件，防止在氧化处理之后产生的各向异性热蚀刻的多晶硅化物层的侧壁穿透根据本发明的半导体器件的间隔物 发明。

公开(公告)号：US06713806B2

公开(公告)日：2004-03-30

申请号：US10132301

申请日：2002-04-26

申请人： Jong-Bor Wang ,  Chii-Ming Shiah

发明人： Jong-Bor Wang ,  Chii-Ming Shiah

IPC分类号： H01L21311

CPC分类号： H01L28/91 ,  H01L21/2885 ,  H01L21/32134 ,  H01L27/10855 ,  H01L28/55

摘要： This is related to a method for the manufacture of a capacitor with wing extensions and the capacitor device. The method comprises: (1) causing multiple contact areas to be disposed in alternate positions, such that two adjacent contact areas are complements of each other, (2) depositing electroplating base material (EBM) over the contact area, (3) electroplating a conductive material on the sidewalls of the EBM slab to form plate electrode; and then (4) etching back the EBM leaving only the electrode portion. The capacitor formed by the above method has a larger surface area on the electrode compared with that made by the conventional method, and the cell capacitance is also better. This method is especially effective for the manufacture of high-density memory device.

摘要翻译： 这涉及制造具有机翼延伸部分的电容器和电容器装置的方法。 该方法包括：（1）使多个接触区域设置在交替位置，使得两个相邻接触区域彼此互补，（2）在接触区域上沉积电镀基材（EBM），（3）电镀a 导电材料在EBM板的侧壁上形成板电极; 然后（4）仅回退EBM，仅留下电极部分。 通过上述方法形成的电容器与常规方法相比具有更大的电极表面积，并且电池电容也更好。 该方法对于高密度存储器件的制造特别有效。