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1.发明申请HIGH PERFORMANCE TWO-PORT SRAM ARCHITECTURE USING 8T HIGH PERFORMANCE SINGLE-PORT BIT CELL 有权高性能双端口SRAM架构使用8T高性能单端口单元公开(公告)号：US20130215689A1
公开(公告)日：2013-08-22
申请号：US13402429
申请日：2012-02-22
IPC分类号： G11C7/22
CPC分类号： G11C11/419 , G11C8/18
摘要： An 8T memory bit cell receives a clock signal and read and write address signals. A read address latch/clock circuit receives the clock signal and the read address signals and initiates a read operation during a first clock cycle state. A write address flip-flop/clock circuit receives the clock signal and the write address signals and initiates a write operation during a second clock cycle state. An inverter receives and inverts the clock signal and applies the inverted clock signal to the write address flip-flop/clock circuit. The read address latch/clock circuit initiates a read word line precharge operation during the second clock cycle state and a write word line precharge operation during the first clock cycle state. The write address flip-flop/clock circuit may also include a loose self-timer to end a write cycle is a clock signal continues beyond a predetermined time.
摘要翻译： 8T存储器单元接收时钟信号并读取和写入地址信号。 读地址锁存/时钟电路接收时钟信号和读地址信号，并在第一时钟周期状态期间启动读操作。 写地址触发器/时钟电路在第二时钟周期状态期间接收时钟信号和写入地址信号并发起写入操作。 逆变器接收并反相时钟信号，并将反相时钟信号施加到写入地址触发器/时钟电路。 读地址锁存/时钟电路在第二时钟周期状态期间启动读字线预充电操作和在第一时钟周期状态期间的写字线预充电操作。 写地址触发器/时钟电路还可以包括松开的自拍以结束写周期是时钟信号持续超过预定时间。
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公开(公告)号：US20110299349A1
公开(公告)日：2011-12-08
申请号：US12794139
申请日：2010-06-04
摘要： A static random access memory (SRAM) and method of evaluating the same for cell stability, write margin, and read current margin. The memory is constructed so that bit line precharge can be disabled, and so that complementary bit lines for each column of cells can float during memory operations. The various tests are performed by precharging the bit lines for a column, then floating the bit lines, and while the bit lines are floating, pulsing the word lines of one or more selected cells to cause the voltage on one of the bit lines to discharge. The discharged bit line voltage is then applied to another cell, which is then read in a normal read operation to determine whether its state changed due to the discharged bit line voltage. The memory can be characterized for cell stability, write margin, and read current margin in this manner; the method can also be adapted into a manufacturing margin screen, or used in failure analysis.
摘要翻译： 一种静态随机存取存储器（SRAM）及其对电池稳定性，写裕度和读取电流裕度的评估方法。 存储器被构造为使得位线预充电可被禁用，并且因此在存储器操作期间，每列单元的互补位线可以浮置。 通过对列的位线进行预充电，然后浮置位线来执行各种测试，并且当位线浮动时，使一个或多个所选单元的字线脉冲以使其中一个位线上的电压放电 。 然后将放电的位线电压施加到另一个单元，然后在正常读取操作中读取，以确定其状态是否由于放电的位线电压而改变。 存储器可以以这种方式表征电池稳定性，写入裕度和读取电流裕度; 该方法也可以适应于制造边界屏幕，或用于故障分析。
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公开(公告)号：US08120439B2
公开(公告)日：2012-02-21
申请号：US12540367
申请日：2009-08-13
CPC分类号： H03B5/06 , H03B2200/0094
摘要： An exemplary fast start-up crystal oscillator with reduced start-up time. The exemplary oscillator reduces the start-up time (i.e., the time taken to attain sustained stable oscillations after the power is turned on) by increasing the negative resistance of a circuit. Increasing the negative resistance increases the rate of growth of the oscillations, thereby reducing start-up time. The exemplary crystal oscillator includes a gain stage with negative resistance. A crystal with shunt capacitance is placed in the feedback loop of the gain stage. A buffer is coupled to the gain stage such that it blocks the crystal shunt capacitance from loading the gain stage, effectively increasing the negative resistance of the gain stage. Further, an oscillation detection and control circuit is coupled between the crystal and the gain stage. The oscillation detection and control circuit connects the buffer during start-up, and disconnects the buffer once an oscillation signal attains sustained stable oscillations.
摘要翻译： 具有降低启动时间的示例性快速启动晶体振荡器。 示例性振荡器通过增加电路的负电阻来减小启动时间（即，在电源接通之后获得持续的稳定振荡所花费的时间）。 增加负电阻会增加振荡的增长率，从而减少启动时间。 示例性晶体振荡器包括具有负电阻的增益级。 具有并联电容的晶体放置在增益级的反馈环路中。 缓冲器耦合到增益级，使得其阻止晶体分流电容加载增益级，有效地增加增益级的负电阻。 此外，振荡检测和控制电路耦合在晶体和增益级之间。 振荡检测和控制电路在启动期间连接缓冲器，一旦振荡信号达到持续的稳定振荡，就断开缓冲器。
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公开(公告)号：US20110216618A1
公开(公告)日：2011-09-08
申请号：US12719616
申请日：2010-03-08
IPC分类号： G11C5/14
CPC分类号： G11C5/14
摘要： Supply voltage compensated tracking circuit in a split-rail static random access memory (SRAM). The circuit includes a tracking circuit for tracking a delay required for generating sense amplifier enable (SE) signal in a memory. The tracking circuit receives an array supply voltage (VDDAR) and a periphery supply voltage (VDDPR). Further, the circuit includes a discharge control circuit, operatively coupled to the tracking circuit, for increasing delay in activating a first transistor of the tracking circuit when VDDAR is higher than VDDPR; and a contention circuit including an output coupled to the first transistor, for delaying a discharge path activation through the first transistor when VDDAR is lower than the VDDPR.
摘要翻译： 分立轨静态随机存取存储器（SRAM）中的电源补偿跟踪电路。 电路包括用于跟踪在存储器中产生读出放大器使能（SE）信号所需的延迟的跟踪电路。 跟踪电路接收阵列电源电压（VDDAR）和外围电源电压（VDDPR）。 此外，电路包括可操作地耦合到跟踪电路的放电控制电路，用于当VDDAR高于VDDPR时增加激活跟踪电路的第一晶体管的延迟; 以及竞争电路，其包括耦合到所述第一晶体管的输出，用于当VDDAR低于所述VDDPR时延迟通过所述第一晶体管的放电路径激活。
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5.发明授权High performance two-port SRAM architecture using 8T high performance single port bit cell 有权高性能双端口SRAM架构采用8T高性能单端口位单元公开(公告)号：US08958254B2
公开(公告)日：2015-02-17
申请号：US13402429
申请日：2012-02-22
IPC分类号： G11C7/00
CPC分类号： G11C11/419 , G11C8/18
摘要： An 8T memory bit cell receives a clock signal and read and write address signals. A read address latch/clock circuit receives the clock signal and the read address signals and initiates a read operation during a first clock cycle state. A write address flip-flop/clock circuit receives the clock signal and the write address signals and initiates a write operation during a second clock cycle state. An inverter receives and inverts the clock signal and applies the inverted clock signal to the write address flip-flop/clock circuit. The read address latch/clock circuit initiates a read word line precharge operation during the second clock cycle state and a write word line precharge operation during the first clock cycle state. The write address flip-flop/clock circuit may also include a loose self-timer to end a write cycle is a clock signal continues beyond a predetermined time.
摘要翻译： 8T存储器单元接收时钟信号并读取和写入地址信号。 读地址锁存/时钟电路接收时钟信号和读地址信号，并在第一时钟周期状态期间启动读操作。 写地址触发器/时钟电路在第二时钟周期状态期间接收时钟信号和写入地址信号并发起写入操作。 逆变器接收并反相时钟信号，并将反相时钟信号施加到写入地址触发器/时钟电路。 读地址锁存/时钟电路在第二时钟周期状态期间启动读字线预充电操作和在第一时钟周期状态期间的写字线预充电操作。 写地址触发器/时钟电路还可以包括松开的自拍以结束写周期是时钟信号持续超过预定时间。
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公开(公告)号：US08284626B2
公开(公告)日：2012-10-09
申请号：US12719616
申请日：2010-03-08
IPC分类号： G11C7/00
CPC分类号： G11C5/14
摘要： Supply voltage compensated tracking circuit in a split-rail static random access memory (SRAM). The circuit includes a tracking circuit for tracking a delay required for generating sense amplifier enable (SE) signal in a memory. The tracking circuit receives an array supply voltage (VDDAR) and a periphery supply voltage (VDDPR). Further, the circuit includes a discharge control circuit, operatively coupled to the tracking circuit, for increasing delay in activating a first transistor of the tracking circuit when VDDAR is higher than VDDPR; and a contention circuit including an output coupled to the first transistor, for delaying a discharge path activation through the first transistor when VDDAR is lower than the VDDPR.
摘要翻译： 分立轨静态随机存取存储器（SRAM）中的电源补偿跟踪电路。 电路包括用于跟踪在存储器中产生读出放大器使能（SE）信号所需的延迟的跟踪电路。 跟踪电路接收阵列电源电压（VDDAR）和外围电源电压（VDDPR）。 此外，电路包括可操作地耦合到跟踪电路的放电控制电路，用于当VDDAR高于VDDPR时增加激活跟踪电路的第一晶体管的延迟; 以及竞争电路，其包括耦合到所述第一晶体管的输出，用于当VDDAR低于所述VDDPR时延迟通过所述第一晶体管的放电路径激活。
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公开(公告)号：US08228749B2
公开(公告)日：2012-07-24
申请号：US12794139
申请日：2010-06-04
摘要： A static random access memory (SRAM) and method of evaluating the same for cell stability, write margin, and read current margin. The memory is constructed so that bit line precharge can be disabled, and so that complementary bit lines for each column of cells can float during memory operations. The various tests are performed by precharging the bit lines for a column, then floating the bit lines, and while the bit lines are floating, pulsing the word lines of one or more selected cells to cause the voltage on one of the bit lines to discharge. The discharged bit line voltage is then applied to another cell, which is then read in a normal read operation to determine whether its state changed due to the discharged bit line voltage. The memory can be characterized for cell stability, write margin, and read current margin in this manner; the method can also be adapted into a manufacturing margin screen, or used in failure analysis.
摘要翻译： 一种静态随机存取存储器（SRAM）及其对电池稳定性，写裕度和读取电流裕度的评估方法。 存储器被构造为使得位线预充电可被禁用，并且因此在存储器操作期间，每列单元的互补位线可以浮置。 通过对列的位线进行预充电，然后浮置位线来执行各种测试，并且当位线浮动时，使一个或多个所选单元的字线脉冲以使其中一个位线上的电压放电 。 然后将放电的位线电压施加到另一个单元，然后在正常读取操作中读取，以确定其状态是否由于放电的位线电压而改变。 存储器可以以这种方式表征电池稳定性，写入裕度和读取电流裕度; 该方法也可以适应于制造边界屏幕，或用于故障分析。
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公开(公告)号：US20110037527A1
公开(公告)日：2011-02-17
申请号：US12540367
申请日：2009-08-13
IPC分类号： H03B5/30
CPC分类号： H03B5/06 , H03B2200/0094
摘要： An exemplary fast start-up crystal oscillator with reduced start-up time. The exemplary oscillator reduces the start-up time (i.e., the time taken to attain sustained stable oscillations after the power is turned on) by increasing the negative resistance of a circuit. Increasing the negative resistance increases the rate of growth of the oscillations, thereby reducing start-up time. The exemplary crystal oscillator includes a gain stage with negative resistance. A crystal with shunt capacitance is placed in the feedback loop of the gain stage. A buffer is coupled to the gain stage such that it blocks the crystal shunt capacitance from loading the gain stage, effectively increasing the negative resistance of the gain stage. Further, an oscillation detection and control circuit is coupled between the crystal and the gain stage. The oscillation detection and control circuit connects the buffer during start-up, and disconnects the buffer once an oscillation signal attains sustained stable oscillations.
摘要翻译： 具有降低启动时间的示例性快速启动晶体振荡器。 示例性振荡器通过增加电路的负电阻来减小启动时间（即，在电源接通之后获得持续的稳定振荡所花费的时间）。 增加负电阻会增加振荡的增长率，从而减少启动时间。 示例性晶体振荡器包括具有负电阻的增益级。 具有并联电容的晶体放置在增益级的反馈环路中。 缓冲器耦合到增益级，使得其阻止晶体分流电容加载增益级，有效地增加增益级的负电阻。 此外，振荡检测和控制电路耦合在晶体和增益级之间。 振荡检测和控制电路在启动期间连接缓冲器，一旦振荡信号达到持续的稳定振荡，就断开缓冲器。
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